RISC-V pmpcfg13 CSR Register

PMP entry 52 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr52 may still be locked by a later locked TOR entry.

PMP entry 52 is locked; writes to pmp52cfg and pmpaddr52 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr51 is also locked.

PMP entry 52 is disabled and matches no addresses.

PMP entry 52 uses top-of-range matching; the upper bound comes from pmpaddr52, and the lower bound comes from pmpaddr51.

PMP entry 52 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 52 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr52.

PMP entry 52 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 52 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 52 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 52 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 52 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 52 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 53 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr53 may still be locked by a later locked TOR entry.

PMP entry 53 is locked; writes to pmp53cfg and pmpaddr53 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr52 is also locked.

PMP entry 53 is disabled and matches no addresses.

PMP entry 53 uses top-of-range matching; the upper bound comes from pmpaddr53, and the lower bound comes from pmpaddr52.

PMP entry 53 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 53 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr53.

PMP entry 53 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 53 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 53 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 53 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 53 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 53 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 54 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr54 may still be locked by a later locked TOR entry.

PMP entry 54 is locked; writes to pmp54cfg and pmpaddr54 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr53 is also locked.

PMP entry 54 is disabled and matches no addresses.

PMP entry 54 uses top-of-range matching; the upper bound comes from pmpaddr54, and the lower bound comes from pmpaddr53.

PMP entry 54 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 54 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr54.

PMP entry 54 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 54 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 54 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 54 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 54 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 54 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 55 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr55 may still be locked by a later locked TOR entry.

PMP entry 55 is locked; writes to pmp55cfg and pmpaddr55 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr54 is also locked.

PMP entry 55 is disabled and matches no addresses.

PMP entry 55 uses top-of-range matching; the upper bound comes from pmpaddr55, and the lower bound comes from pmpaddr54.

PMP entry 55 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 55 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr55.

PMP entry 55 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 55 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 55 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 55 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 55 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 55 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.