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CSR Bit Fields

RISC-V pmpcfg14 CSR Register

Address 0x3AEPrivilege MachineAccess RW / MXLEN: 32 bits on RV32; 64 bits on RV64Machine physical memory protection CSRs

pmpcfg14 (0x3AE) is a machine PMP configuration CSR packing pmp56cfg-pmp59cfg on RV32 and pmp56cfg-pmp63cfg on RV64.

Related Search Terms
pmpcfg14 CSRpmpcfg14 0x3AEPMP R W XPMP A fieldPMP L bitPMP entries 56-63
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
pmp63cfg.L63WARL/may be RO0pmp56cfg.R0Collective WARL (R/W/X)
Field Map

Understand pmpcfg14 By Bit Fields

48 key fields
7

pmp56cfg.L

WARL/may be RO0

Lock bit for PMP entry 56. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp56cfg.L (bit 7) — Lock bit for PMP entry 56. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 56. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp56cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
6:5

pmp56cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp56cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp56cfg.reserved (bits 6:5) — Bits 6:5 of pmp56cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp56cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
4:3

pmp56cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 56. This field is WARL and may be implemented as read-only zero.

pmp56cfg.A (bits 4:3) — Address-matching mode for PMP entry 56. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 56. This field is WARL and may be implemented as read-only zero.

Common Values

pmp56cfg.A
0OFF

PMP entry 56 is disabled and matches no addresses.

1TOR

PMP entry 56 uses top-of-range matching; the upper bound comes from pmpaddr56, and the lower bound comes from pmpaddr55.

2NA4

PMP entry 56 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 56 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr56.

↗Open Official Manual
2

pmp56cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 56; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp56cfg.X (bit 2) — X bit for PMP entry 56; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 56; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp56cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
1

pmp56cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 56; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp56cfg.W (bit 1) — W bit for PMP entry 56; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 56; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp56cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
0

pmp56cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 56; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp56cfg.R (bit 0) — R bit for PMP entry 56; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 56; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp56cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
15

pmp57cfg.L

WARL/may be RO0

Lock bit for PMP entry 57. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp57cfg.L (bit 15) — Lock bit for PMP entry 57. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 57. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp57cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
14:13

pmp57cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp57cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp57cfg.reserved (bits 14:13) — Bits 6:5 of pmp57cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp57cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
12:11

pmp57cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 57. This field is WARL and may be implemented as read-only zero.

pmp57cfg.A (bits 12:11) — Address-matching mode for PMP entry 57. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 57. This field is WARL and may be implemented as read-only zero.

Common Values

pmp57cfg.A
0OFF

PMP entry 57 is disabled and matches no addresses.

1TOR

PMP entry 57 uses top-of-range matching; the upper bound comes from pmpaddr57, and the lower bound comes from pmpaddr56.

2NA4

PMP entry 57 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 57 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr57.

↗Open Official Manual
10

pmp57cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 57; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp57cfg.X (bit 10) — X bit for PMP entry 57; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 57; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp57cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
9

pmp57cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 57; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp57cfg.W (bit 9) — W bit for PMP entry 57; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 57; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp57cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
8

pmp57cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 57; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp57cfg.R (bit 8) — R bit for PMP entry 57; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 57; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp57cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
23

pmp58cfg.L

WARL/may be RO0

Lock bit for PMP entry 58. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp58cfg.L (bit 23) — Lock bit for PMP entry 58. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 58. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp58cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
22:21

pmp58cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp58cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp58cfg.reserved (bits 22:21) — Bits 6:5 of pmp58cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp58cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
20:19

pmp58cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 58. This field is WARL and may be implemented as read-only zero.

pmp58cfg.A (bits 20:19) — Address-matching mode for PMP entry 58. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 58. This field is WARL and may be implemented as read-only zero.

Common Values

pmp58cfg.A
0OFF

PMP entry 58 is disabled and matches no addresses.

1TOR

PMP entry 58 uses top-of-range matching; the upper bound comes from pmpaddr58, and the lower bound comes from pmpaddr57.

2NA4

PMP entry 58 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 58 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr58.

↗Open Official Manual
18

pmp58cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 58; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp58cfg.X (bit 18) — X bit for PMP entry 58; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 58; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp58cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
17

pmp58cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 58; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp58cfg.W (bit 17) — W bit for PMP entry 58; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 58; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp58cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
16

pmp58cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 58; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp58cfg.R (bit 16) — R bit for PMP entry 58; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 58; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp58cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
31

pmp59cfg.L

WARL/may be RO0

Lock bit for PMP entry 59. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp59cfg.L (bit 31) — Lock bit for PMP entry 59. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 59. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp59cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
30:29

pmp59cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp59cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp59cfg.reserved (bits 30:29) — Bits 6:5 of pmp59cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp59cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
28:27

pmp59cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 59. This field is WARL and may be implemented as read-only zero.

pmp59cfg.A (bits 28:27) — Address-matching mode for PMP entry 59. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 59. This field is WARL and may be implemented as read-only zero.

Common Values

pmp59cfg.A
0OFF

PMP entry 59 is disabled and matches no addresses.

1TOR

PMP entry 59 uses top-of-range matching; the upper bound comes from pmpaddr59, and the lower bound comes from pmpaddr58.

2NA4

PMP entry 59 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 59 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr59.

↗Open Official Manual
26

pmp59cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 59; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp59cfg.X (bit 26) — X bit for PMP entry 59; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 59; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp59cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
25

pmp59cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 59; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp59cfg.W (bit 25) — W bit for PMP entry 59; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 59; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp59cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
24

pmp59cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 59; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp59cfg.R (bit 24) — R bit for PMP entry 59; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 59; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp59cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
39

pmp60cfg.L

WARL/may be RO0

Lock bit for PMP entry 60. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp60cfg.L (bit 39) — Lock bit for PMP entry 60. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 60. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp60cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
38:37

pmp60cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp60cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp60cfg.reserved (bits 38:37) — Bits 6:5 of pmp60cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp60cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
36:35

pmp60cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 60. This field is WARL and may be implemented as read-only zero.

pmp60cfg.A (bits 36:35) — Address-matching mode for PMP entry 60. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 60. This field is WARL and may be implemented as read-only zero.

Common Values

pmp60cfg.A
0OFF

PMP entry 60 is disabled and matches no addresses.

1TOR

PMP entry 60 uses top-of-range matching; the upper bound comes from pmpaddr60, and the lower bound comes from pmpaddr59.

2NA4

PMP entry 60 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 60 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr60.

↗Open Official Manual
34

pmp60cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 60; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp60cfg.X (bit 34) — X bit for PMP entry 60; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 60; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp60cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
33

pmp60cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 60; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp60cfg.W (bit 33) — W bit for PMP entry 60; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 60; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp60cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
32

pmp60cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 60; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp60cfg.R (bit 32) — R bit for PMP entry 60; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 60; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp60cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
47

pmp61cfg.L

WARL/may be RO0

Lock bit for PMP entry 61. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp61cfg.L (bit 47) — Lock bit for PMP entry 61. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 61. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp61cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
46:45

pmp61cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp61cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp61cfg.reserved (bits 46:45) — Bits 6:5 of pmp61cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp61cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
44:43

pmp61cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 61. This field is WARL and may be implemented as read-only zero.

pmp61cfg.A (bits 44:43) — Address-matching mode for PMP entry 61. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 61. This field is WARL and may be implemented as read-only zero.

Common Values

pmp61cfg.A
0OFF

PMP entry 61 is disabled and matches no addresses.

1TOR

PMP entry 61 uses top-of-range matching; the upper bound comes from pmpaddr61, and the lower bound comes from pmpaddr60.

2NA4

PMP entry 61 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 61 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr61.

↗Open Official Manual
42

pmp61cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 61; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp61cfg.X (bit 42) — X bit for PMP entry 61; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 61; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp61cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
41

pmp61cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 61; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp61cfg.W (bit 41) — W bit for PMP entry 61; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 61; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp61cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
40

pmp61cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 61; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp61cfg.R (bit 40) — R bit for PMP entry 61; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 61; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp61cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
55

pmp62cfg.L

WARL/may be RO0

Lock bit for PMP entry 62. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp62cfg.L (bit 55) — Lock bit for PMP entry 62. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 62. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp62cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
54:53

pmp62cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp62cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp62cfg.reserved (bits 54:53) — Bits 6:5 of pmp62cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp62cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
52:51

pmp62cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 62. This field is WARL and may be implemented as read-only zero.

pmp62cfg.A (bits 52:51) — Address-matching mode for PMP entry 62. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 62. This field is WARL and may be implemented as read-only zero.

Common Values

pmp62cfg.A
0OFF

PMP entry 62 is disabled and matches no addresses.

1TOR

PMP entry 62 uses top-of-range matching; the upper bound comes from pmpaddr62, and the lower bound comes from pmpaddr61.

2NA4

PMP entry 62 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 62 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr62.

↗Open Official Manual
50

pmp62cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 62; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp62cfg.X (bit 50) — X bit for PMP entry 62; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 62; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp62cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
49

pmp62cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 62; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp62cfg.W (bit 49) — W bit for PMP entry 62; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 62; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp62cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
48

pmp62cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 62; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp62cfg.R (bit 48) — R bit for PMP entry 62; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 62; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp62cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
63

pmp63cfg.L

WARL/may be RO0

Lock bit for PMP entry 63. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp63cfg.L (bit 63) — Lock bit for PMP entry 63. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 63. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp63cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
62:61

pmp63cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp63cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp63cfg.reserved (bits 62:61) — Bits 6:5 of pmp63cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp63cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
60:59

pmp63cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 63. This field is WARL and may be implemented as read-only zero.

pmp63cfg.A (bits 60:59) — Address-matching mode for PMP entry 63. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 63. This field is WARL and may be implemented as read-only zero.

Common Values

pmp63cfg.A
0OFF

PMP entry 63 is disabled and matches no addresses.

1TOR

PMP entry 63 uses top-of-range matching; the upper bound comes from pmpaddr63, and the lower bound comes from pmpaddr62.

2NA4

PMP entry 63 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 63 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr63.

↗Open Official Manual
58

pmp63cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 63; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp63cfg.X (bit 58) — X bit for PMP entry 63; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 63; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp63cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
57

pmp63cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 63; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp63cfg.W (bit 57) — W bit for PMP entry 63; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 63; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp63cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
56

pmp63cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 63; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp63cfg.R (bit 56) — R bit for PMP entry 63; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 63; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp63cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
Official Basis & Search Notes

pmpcfg14 packs four 8-bit PMP configurations on RV32 and eight on RV64; each contains L, A, X, W, R, and two reserved zero bits.

The Machine ISA Physical Memory Protection CSRs subsection defines the address, MXLEN packing, M-mode-only access, and WARL/RO0 behavior.
A encodes OFF, TOR, NA4, or NAPOT; platform grain may make NA4 unselectable.
Base PMP and Smepmp with MML=1 interpret L/R/W/X differently, so field values must be read with mseccfg state.
RISC-V ISA Manual 2026-07-09 release - Machine ISA PMPRISC-V Privileged Architecture - Physical Memory ProtectionRISC-V Privileged Architecture - Smepmp Physical Memory Protection Rules

What To Check First When Reading This CSR

  • - pmpcfg14 contains entries 56-59 on RV32 and entries 56-63 in the same CSR on RV64.
  • - PMP is optional; implementations may provide 0, 16, or 64 entries, and every PMP CSR field is WARL and may be read-only zero.
  • - PMP CSRs are accessible only to M-mode.
  • - The M-mode permission bypass described on this page applies only when effective privilege is M; mstatus.MPRV can make an M-mode data access undergo PMP checks with effective S/U privilege.
  • - At reset, writable PMP A and L fields become 0 unless the platform mandates different values for some PMP registers; other PMP field reset values are unspecified, but no WARL field contains an illegal value.

Risk Checks Before Writing

  • - R/W/X form one collective WARL field. In base PMP (mseccfg.MML=0), combinations with R=0 and W=1 are reserved; Smepmp collectively reinterprets L/R/W/X when MML=1.
  • - L=1 locks pmpNcfg and pmpaddrN until hart reset; with A=TOR it also locks the preceding pmpaddr. Smepmp mseccfg.RLB can bypass locking rules.
  • - Read back WARL fields after writing; do not assume an unimplemented permission or matching mode is accepted.

Put It Back Into A Real Flow

1

Choose OFF, TOR, NA4, or NAPOT in A and encode the range in pmpaddrN (and the preceding address register for TOR).

2

Interpret and write the collective WARL L/R/W/X encoding according to the current mseccfg.MML state.

3

Read back pmpcfg and pmpaddr to confirm the implemented WARL values; set L only after finalizing the configuration.

FAQ

Does pmpcfg14 contain the same number of entries on RV32 and RV64?

No. RV32 pmpcfg14 packs pmp56cfg-pmp59cfg, while RV64 pmpcfg14 packs pmp56cfg-pmp63cfg.