CSR Bit Fields

RISC-V pmpcfg15 CSR Register

Address 0x3AFPrivilege MachineAccess RW / RV32 only / 32-bitMachine physical memory protection CSRs

pmpcfg15 is an RV32-only physical memory protection configuration CSR; odd-numbered pmpcfg CSRs are illegal on RV64.

Field Map

Understand pmpcfg15 By Bit Fields

24 key fields
7

pmp60cfg.L

RW

Lock bit for PMP entry 60.

pmp60cfg.L (bit 7) — Lock bit for PMP entry 60.

What This Field Controls

  • - Lock bit for PMP entry 60.

Common Values

pmp60cfg.L
0Unlocked

PMP entry 60 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr60 may still be locked by a later locked TOR entry.

1Locked

PMP entry 60 is locked; writes to pmp60cfg and pmpaddr60 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr59 is also locked.

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6:5

pmp60cfg.reserved

RO

Reserved bits for PMP entry 60; writes follow WARL/reserved-bit rules.

pmp60cfg.reserved (bits 6:5) — Reserved bits for PMP entry 60; writes follow WARL/reserved-bit rules.

What This Field Controls

  • - Reserved bits for PMP entry 60; writes follow WARL/reserved-bit rules.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Open Official Manual
4:3

pmp60cfg.A

RW

Address-matching mode for PMP entry 60.

pmp60cfg.A (bits 4:3) — Address-matching mode for PMP entry 60.

What This Field Controls

  • - Address-matching mode for PMP entry 60.

Common Values

pmp60cfg.A
0OFF

PMP entry 60 is disabled and matches no addresses.

1TOR

PMP entry 60 uses top-of-range matching; the upper bound comes from pmpaddr60, and the lower bound comes from pmpaddr59.

2NA4

PMP entry 60 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 60 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr60.

Open Official Manual
2

pmp60cfg.X

RW

Execute permission for PMP entry 60.

pmp60cfg.X (bit 2) — Execute permission for PMP entry 60.

What This Field Controls

  • - Execute permission for PMP entry 60.

Common Values

pmp60cfg.X
0Execute denied

PMP entry 60 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

1Execute permitted

PMP entry 60 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

Open Official Manual
1

pmp60cfg.W

RW

Write permission for PMP entry 60.

pmp60cfg.W (bit 1) — Write permission for PMP entry 60.

What This Field Controls

  • - Write permission for PMP entry 60.

Common Values

pmp60cfg.W
0Write denied

PMP entry 60 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

1Write permitted (requires R=1)

PMP entry 60 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

Open Official Manual
0

pmp60cfg.R

RW

Read permission for PMP entry 60.

pmp60cfg.R (bit 0) — Read permission for PMP entry 60.

What This Field Controls

  • - Read permission for PMP entry 60.

Common Values

pmp60cfg.R
0Read denied

PMP entry 60 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

1Read permitted

PMP entry 60 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

Open Official Manual
15

pmp61cfg.L

RW

Lock bit for PMP entry 61.

pmp61cfg.L (bit 15) — Lock bit for PMP entry 61.

What This Field Controls

  • - Lock bit for PMP entry 61.

Common Values

pmp61cfg.L
0Unlocked

PMP entry 61 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr61 may still be locked by a later locked TOR entry.

1Locked

PMP entry 61 is locked; writes to pmp61cfg and pmpaddr61 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr60 is also locked.

Open Official Manual
14:13

pmp61cfg.reserved

RO

Reserved bits for PMP entry 61; writes follow WARL/reserved-bit rules.

pmp61cfg.reserved (bits 14:13) — Reserved bits for PMP entry 61; writes follow WARL/reserved-bit rules.

What This Field Controls

  • - Reserved bits for PMP entry 61; writes follow WARL/reserved-bit rules.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Open Official Manual
12:11

pmp61cfg.A

RW

Address-matching mode for PMP entry 61.

pmp61cfg.A (bits 12:11) — Address-matching mode for PMP entry 61.

What This Field Controls

  • - Address-matching mode for PMP entry 61.

Common Values

pmp61cfg.A
0OFF

PMP entry 61 is disabled and matches no addresses.

1TOR

PMP entry 61 uses top-of-range matching; the upper bound comes from pmpaddr61, and the lower bound comes from pmpaddr60.

2NA4

PMP entry 61 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 61 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr61.

Open Official Manual
10

pmp61cfg.X

RW

Execute permission for PMP entry 61.

pmp61cfg.X (bit 10) — Execute permission for PMP entry 61.

What This Field Controls

  • - Execute permission for PMP entry 61.

Common Values

pmp61cfg.X
0Execute denied

PMP entry 61 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

1Execute permitted

PMP entry 61 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

Open Official Manual
9

pmp61cfg.W

RW

Write permission for PMP entry 61.

pmp61cfg.W (bit 9) — Write permission for PMP entry 61.

What This Field Controls

  • - Write permission for PMP entry 61.

Common Values

pmp61cfg.W
0Write denied

PMP entry 61 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

1Write permitted (requires R=1)

PMP entry 61 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

Open Official Manual
8

pmp61cfg.R

RW

Read permission for PMP entry 61.

pmp61cfg.R (bit 8) — Read permission for PMP entry 61.

What This Field Controls

  • - Read permission for PMP entry 61.

Common Values

pmp61cfg.R
0Read denied

PMP entry 61 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

1Read permitted

PMP entry 61 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

Open Official Manual
23

pmp62cfg.L

RW

Lock bit for PMP entry 62.

pmp62cfg.L (bit 23) — Lock bit for PMP entry 62.

What This Field Controls

  • - Lock bit for PMP entry 62.

Common Values

pmp62cfg.L
0Unlocked

PMP entry 62 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr62 may still be locked by a later locked TOR entry.

1Locked

PMP entry 62 is locked; writes to pmp62cfg and pmpaddr62 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr61 is also locked.

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22:21

pmp62cfg.reserved

RO

Reserved bits for PMP entry 62; writes follow WARL/reserved-bit rules.

pmp62cfg.reserved (bits 22:21) — Reserved bits for PMP entry 62; writes follow WARL/reserved-bit rules.

What This Field Controls

  • - Reserved bits for PMP entry 62; writes follow WARL/reserved-bit rules.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Open Official Manual
20:19

pmp62cfg.A

RW

Address-matching mode for PMP entry 62.

pmp62cfg.A (bits 20:19) — Address-matching mode for PMP entry 62.

What This Field Controls

  • - Address-matching mode for PMP entry 62.

Common Values

pmp62cfg.A
0OFF

PMP entry 62 is disabled and matches no addresses.

1TOR

PMP entry 62 uses top-of-range matching; the upper bound comes from pmpaddr62, and the lower bound comes from pmpaddr61.

2NA4

PMP entry 62 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 62 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr62.

Open Official Manual
18

pmp62cfg.X

RW

Execute permission for PMP entry 62.

pmp62cfg.X (bit 18) — Execute permission for PMP entry 62.

What This Field Controls

  • - Execute permission for PMP entry 62.

Common Values

pmp62cfg.X
0Execute denied

PMP entry 62 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

1Execute permitted

PMP entry 62 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

Open Official Manual
17

pmp62cfg.W

RW

Write permission for PMP entry 62.

pmp62cfg.W (bit 17) — Write permission for PMP entry 62.

What This Field Controls

  • - Write permission for PMP entry 62.

Common Values

pmp62cfg.W
0Write denied

PMP entry 62 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

1Write permitted (requires R=1)

PMP entry 62 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

Open Official Manual
16

pmp62cfg.R

RW

Read permission for PMP entry 62.

pmp62cfg.R (bit 16) — Read permission for PMP entry 62.

What This Field Controls

  • - Read permission for PMP entry 62.

Common Values

pmp62cfg.R
0Read denied

PMP entry 62 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

1Read permitted

PMP entry 62 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

Open Official Manual
31

pmp63cfg.L

RW

Lock bit for PMP entry 63.

pmp63cfg.L (bit 31) — Lock bit for PMP entry 63.

What This Field Controls

  • - Lock bit for PMP entry 63.

Common Values

pmp63cfg.L
0Unlocked

PMP entry 63 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Entry 63 is the last PMP entry, so there is no later TOR entry that can lock pmpaddr63.

1Locked

PMP entry 63 is locked; writes to pmp63cfg and pmpaddr63 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr62 is also locked.

Open Official Manual
30:29

pmp63cfg.reserved

RO

Reserved bits for PMP entry 63; writes follow WARL/reserved-bit rules.

pmp63cfg.reserved (bits 30:29) — Reserved bits for PMP entry 63; writes follow WARL/reserved-bit rules.

What This Field Controls

  • - Reserved bits for PMP entry 63; writes follow WARL/reserved-bit rules.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Open Official Manual
28:27

pmp63cfg.A

RW

Address-matching mode for PMP entry 63.

pmp63cfg.A (bits 28:27) — Address-matching mode for PMP entry 63.

What This Field Controls

  • - Address-matching mode for PMP entry 63.

Common Values

pmp63cfg.A
0OFF

PMP entry 63 is disabled and matches no addresses.

1TOR

PMP entry 63 uses top-of-range matching; the upper bound comes from pmpaddr63, and the lower bound comes from pmpaddr62.

2NA4

PMP entry 63 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 63 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr63.

Open Official Manual
26

pmp63cfg.X

RW

Execute permission for PMP entry 63.

pmp63cfg.X (bit 26) — Execute permission for PMP entry 63.

What This Field Controls

  • - Execute permission for PMP entry 63.

Common Values

pmp63cfg.X
0Execute denied

PMP entry 63 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

1Execute permitted

PMP entry 63 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

Open Official Manual
25

pmp63cfg.W

RW

Write permission for PMP entry 63.

pmp63cfg.W (bit 25) — Write permission for PMP entry 63.

What This Field Controls

  • - Write permission for PMP entry 63.

Common Values

pmp63cfg.W
0Write denied

PMP entry 63 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

1Write permitted (requires R=1)

PMP entry 63 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

Open Official Manual
24

pmp63cfg.R

RW

Read permission for PMP entry 63.

pmp63cfg.R (bit 24) — Read permission for PMP entry 63.

What This Field Controls

  • - Read permission for PMP entry 63.

Common Values

pmp63cfg.R
0Read denied

PMP entry 63 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

1Read permitted

PMP entry 63 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

Open Official Manual

What To Check First When Reading This CSR

  • - First confirm that the current hart implements pmpcfg15; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
  • - Use address 0x3AF and the lowest access privilege (Machine) to decide whether software may read it directly.
  • - Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

  • - Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
  • - Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.

Put It Back Into A Real Flow

1

During initialization or the relevant privileged flow, software reads pmpcfg15 to observe the current state.

2

Modify only the target fields while preserving all other bits.

3

Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.