RISC-V pmpcfg15 CSR Register

PMP entry 60 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr60 may still be locked by a later locked TOR entry.

PMP entry 60 is locked; writes to pmp60cfg and pmpaddr60 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr59 is also locked.

PMP entry 60 is disabled and matches no addresses.

PMP entry 60 uses top-of-range matching; the upper bound comes from pmpaddr60, and the lower bound comes from pmpaddr59.

PMP entry 60 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 60 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr60.

PMP entry 60 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 60 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 60 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 60 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 60 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 60 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 61 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr61 may still be locked by a later locked TOR entry.

PMP entry 61 is locked; writes to pmp61cfg and pmpaddr61 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr60 is also locked.

PMP entry 61 is disabled and matches no addresses.

PMP entry 61 uses top-of-range matching; the upper bound comes from pmpaddr61, and the lower bound comes from pmpaddr60.

PMP entry 61 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 61 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr61.

PMP entry 61 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 61 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 61 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 61 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 61 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 61 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 62 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr62 may still be locked by a later locked TOR entry.

PMP entry 62 is locked; writes to pmp62cfg and pmpaddr62 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr61 is also locked.

PMP entry 62 is disabled and matches no addresses.

PMP entry 62 uses top-of-range matching; the upper bound comes from pmpaddr62, and the lower bound comes from pmpaddr61.

PMP entry 62 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 62 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr62.

PMP entry 62 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 62 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 62 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 62 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 62 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 62 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 63 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Entry 63 is the last PMP entry, so there is no later TOR entry that can lock pmpaddr63.

PMP entry 63 is locked; writes to pmp63cfg and pmpaddr63 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr62 is also locked.

PMP entry 63 is disabled and matches no addresses.

PMP entry 63 uses top-of-range matching; the upper bound comes from pmpaddr63, and the lower bound comes from pmpaddr62.

PMP entry 63 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 63 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr63.

PMP entry 63 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 63 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 63 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 63 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 63 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 63 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.