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CSR Bit Fields

RISC-V pmpcfg15 CSR Register

Address 0x3AFPrivilege MachineAccess RW / RV32 only: 32-bit; access is illegal on RV64Machine physical memory protection CSRs

pmpcfg15 (0x3AF) is the 32-bit RV32 machine PMP configuration CSR packing pmp60cfg-pmp63cfg; access to this odd-numbered CSR is illegal on RV64.

Related Search Terms
pmpcfg15 CSRpmpcfg15 0x3AFPMP R W XPMP A fieldPMP L bitRV32 pmpcfg15
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
pmp63cfg.L31WARL/may be RO0pmp60cfg.R0Collective WARL (R/W/X)
Field Map

Understand pmpcfg15 By Bit Fields

24 key fields
7

pmp60cfg.L

WARL/may be RO0

Lock bit for PMP entry 60. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp60cfg.L (bit 7) — Lock bit for PMP entry 60. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 60. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp60cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
6:5

pmp60cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp60cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp60cfg.reserved (bits 6:5) — Bits 6:5 of pmp60cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp60cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
4:3

pmp60cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 60. This field is WARL and may be implemented as read-only zero.

pmp60cfg.A (bits 4:3) — Address-matching mode for PMP entry 60. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 60. This field is WARL and may be implemented as read-only zero.

Common Values

pmp60cfg.A
0OFF

PMP entry 60 is disabled and matches no addresses.

1TOR

PMP entry 60 uses top-of-range matching; the upper bound comes from pmpaddr60, and the lower bound comes from pmpaddr59.

2NA4

PMP entry 60 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 60 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr60.

↗Open Official Manual
2

pmp60cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 60; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp60cfg.X (bit 2) — X bit for PMP entry 60; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 60; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp60cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
1

pmp60cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 60; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp60cfg.W (bit 1) — W bit for PMP entry 60; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 60; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp60cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
0

pmp60cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 60; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp60cfg.R (bit 0) — R bit for PMP entry 60; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 60; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp60cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
15

pmp61cfg.L

WARL/may be RO0

Lock bit for PMP entry 61. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp61cfg.L (bit 15) — Lock bit for PMP entry 61. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 61. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp61cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
14:13

pmp61cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp61cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp61cfg.reserved (bits 14:13) — Bits 6:5 of pmp61cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp61cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
12:11

pmp61cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 61. This field is WARL and may be implemented as read-only zero.

pmp61cfg.A (bits 12:11) — Address-matching mode for PMP entry 61. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 61. This field is WARL and may be implemented as read-only zero.

Common Values

pmp61cfg.A
0OFF

PMP entry 61 is disabled and matches no addresses.

1TOR

PMP entry 61 uses top-of-range matching; the upper bound comes from pmpaddr61, and the lower bound comes from pmpaddr60.

2NA4

PMP entry 61 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 61 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr61.

↗Open Official Manual
10

pmp61cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 61; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp61cfg.X (bit 10) — X bit for PMP entry 61; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 61; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp61cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
9

pmp61cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 61; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp61cfg.W (bit 9) — W bit for PMP entry 61; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 61; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp61cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
8

pmp61cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 61; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp61cfg.R (bit 8) — R bit for PMP entry 61; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 61; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp61cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
23

pmp62cfg.L

WARL/may be RO0

Lock bit for PMP entry 62. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp62cfg.L (bit 23) — Lock bit for PMP entry 62. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 62. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp62cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
22:21

pmp62cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp62cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp62cfg.reserved (bits 22:21) — Bits 6:5 of pmp62cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp62cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
20:19

pmp62cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 62. This field is WARL and may be implemented as read-only zero.

pmp62cfg.A (bits 20:19) — Address-matching mode for PMP entry 62. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 62. This field is WARL and may be implemented as read-only zero.

Common Values

pmp62cfg.A
0OFF

PMP entry 62 is disabled and matches no addresses.

1TOR

PMP entry 62 uses top-of-range matching; the upper bound comes from pmpaddr62, and the lower bound comes from pmpaddr61.

2NA4

PMP entry 62 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 62 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr62.

↗Open Official Manual
18

pmp62cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 62; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp62cfg.X (bit 18) — X bit for PMP entry 62; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 62; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp62cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
17

pmp62cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 62; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp62cfg.W (bit 17) — W bit for PMP entry 62; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 62; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp62cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
16

pmp62cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 62; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp62cfg.R (bit 16) — R bit for PMP entry 62; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 62; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp62cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
31

pmp63cfg.L

WARL/may be RO0

Lock bit for PMP entry 63. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp63cfg.L (bit 31) — Lock bit for PMP entry 63. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 63. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp63cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
30:29

pmp63cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp63cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp63cfg.reserved (bits 30:29) — Bits 6:5 of pmp63cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp63cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
28:27

pmp63cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 63. This field is WARL and may be implemented as read-only zero.

pmp63cfg.A (bits 28:27) — Address-matching mode for PMP entry 63. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 63. This field is WARL and may be implemented as read-only zero.

Common Values

pmp63cfg.A
0OFF

PMP entry 63 is disabled and matches no addresses.

1TOR

PMP entry 63 uses top-of-range matching; the upper bound comes from pmpaddr63, and the lower bound comes from pmpaddr62.

2NA4

PMP entry 63 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 63 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr63.

↗Open Official Manual
26

pmp63cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 63; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp63cfg.X (bit 26) — X bit for PMP entry 63; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 63; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp63cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
25

pmp63cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 63; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp63cfg.W (bit 25) — W bit for PMP entry 63; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 63; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp63cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
24

pmp63cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 63; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp63cfg.R (bit 24) — R bit for PMP entry 63; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 63; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp63cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
Official Basis & Search Notes

RV32 pmpcfg15 packs pmp60cfg-pmp63cfg as four 8-bit WARL configurations; odd-numbered pmpcfg CSRs are illegal on RV64.

The Machine ISA Physical Memory Protection CSRs subsection defines the address, MXLEN packing, M-mode-only access, and WARL/RO0 behavior.
A encodes OFF, TOR, NA4, or NAPOT; platform grain may make NA4 unselectable.
Base PMP and Smepmp with MML=1 interpret L/R/W/X differently, so field values must be read with mseccfg state.
RISC-V ISA Manual 2026-07-09 release - Machine ISA PMPRISC-V Privileged Architecture - Physical Memory ProtectionRISC-V Privileged Architecture - Smepmp Physical Memory Protection Rules

What To Check First When Reading This CSR

  • - pmpcfg15 exists only on RV32; RV64 uses pmpcfg14 for entries 60-63, and access to pmpcfg15 is illegal.
  • - PMP is optional; implementations may provide 0, 16, or 64 entries, and every PMP CSR field is WARL and may be read-only zero.
  • - PMP CSRs are accessible only to M-mode.
  • - The M-mode permission bypass described on this page applies only when effective privilege is M; mstatus.MPRV can make an M-mode data access undergo PMP checks with effective S/U privilege.
  • - At reset, writable PMP A and L fields become 0 unless the platform mandates different values for some PMP registers; other PMP field reset values are unspecified, but no WARL field contains an illegal value.

Risk Checks Before Writing

  • - R/W/X form one collective WARL field. In base PMP (mseccfg.MML=0), combinations with R=0 and W=1 are reserved; Smepmp collectively reinterprets L/R/W/X when MML=1.
  • - L=1 locks pmpNcfg and pmpaddrN until hart reset; with A=TOR it also locks the preceding pmpaddr. Smepmp mseccfg.RLB can bypass locking rules.
  • - Read back WARL fields after writing; do not assume an unimplemented permission or matching mode is accepted.

Put It Back Into A Real Flow

1

Choose OFF, TOR, NA4, or NAPOT in A and encode the range in pmpaddrN (and the preceding address register for TOR).

2

Interpret and write the collective WARL L/R/W/X encoding according to the current mseccfg.MML state.

3

Read back pmpcfg and pmpaddr to confirm the implemented WARL values; set L only after finalizing the configuration.

FAQ

Can RV64 access pmpcfg15?

No. Odd-numbered pmpcfg CSRs are illegal on RV64; pmpcfg15 packs pmp60cfg-pmp63cfg only on RV32.