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CSR Bit Fields

RISC-V pmpaddr62 CSR Register

Address 0x3EEPrivilege MachineAccess RW / MXLEN: RV32 encodes PA[33:2]; RV64 [53:0] encodes PA[55:2] and [63:54] is zeroMachine physical memory protection CSRs

pmpaddr62 (0x3EE) is the WARL address register for machine PMP entry 62 when 64 PMP entries are implemented; it encodes physical address bits 33:2 on RV32 and 55:2 on RV64.

Related Search Terms
pmpaddr62 CSRpmpaddr62 0x3EEpmpaddr62 TORpmpaddr62 NAPOTpmpaddr62 grainpmp62cfg A
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
063:54WARL/reads zeroaddress[55:2]53:0WARL/may be RO0
Field Map

Understand pmpaddr62 By Bit Fields

2 key fields
63:54

0

WARL/reads zero

RV64: the upper ten bits are zero in the standard pmpaddr format; this segment is part of the WARL format.

0 (bits 63:54) — RV64: the upper ten bits are zero in the standard pmpaddr format; this segment is part of the WARL format.

What This Field Controls

  • - RV64: the upper ten bits are zero in the standard pmpaddr format; this segment is part of the WARL format.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
53:0

address[55:2]

WARL/may be RO0

RV64: encodes bits 55:2 of a 56-bit physical address. Unimplemented physical-address bits make the field WARL; every PMP CSR field may be implemented as read-only zero.

address[55:2] (bits 53:0) — RV64: encodes bits 55:2 of a 56-bit physical address. Unimplemented physical-address bits make the field WARL; every PMP CSR field may be implemented as read-only zero.

What This Field Controls

  • - RV64: encodes bits 55:2 of a 56-bit physical address. Unimplemented physical-address bits make the field WARL; every PMP CSR field may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

pmpaddr62 is the MXLEN-bit WARL address encoding for entry 62 when 64 PMP entries are implemented. pmp62cfg.A determines its meaning; TOR uses pmpaddr61 as the lower bound.

RV32 pmpaddr encodes PA[33:2]; RV64 [53:0] encodes PA[55:2], with [63:54] zero.
TOR entry 62 uses pmpaddr61 as its lower bound and pmpaddr62 as its upper bound; NAPOT uses low pmpaddr62 bits to encode a naturally aligned power-of-two region of at least 8 bytes.
Platform grain changes low-bit readback; pmp62cfg.L or a locked TOR entry 63 can cause writes to pmpaddr62 to be ignored. Smepmp MML=1 changes L's permission meaning, but the relevant L=1 rules remain locked unless RLB=1 temporarily bypasses locking.
RISC-V ISA Manual 2026-07-09 release - Machine ISA PMPRISC-V Privileged Architecture - Physical Memory ProtectionRISC-V Privileged Architecture - Smepmp Physical Memory Protection Rules

What To Check First When Reading This CSR

  • - PMP is optional; implementations may provide 0, 16, or 64 entries, with the lowest-numbered entries implemented first. Therefore, entry 62 is implemented only in a 64-entry implementation; every PMP CSR field is WARL and may be read-only zero.
  • - pmpaddr62 is accessible only to M-mode. Its readback depends on pmp62cfg.A and the platform-wide PMP grain G.
  • - With G>=2 and A=NAPOT, pmpaddr62[G-2:0] reads as ones; with G>=1 and A=OFF/TOR, pmpaddr62[G-1:0] reads as zeros, but those bits do not affect TOR matching. Changing pmp62cfg.A[1] changes readback, not the underlying stored value.
  • - Reset specifies defaults only for writable PMP A/L fields (subject to platform overrides); pmpaddr62's reset value is unspecified, but no WARL field contains an illegal value.

Risk Checks Before Writing

  • - Writes to pmpaddr62 are ignored when pmp62cfg.L=1; pmpaddr62 is also unwritable as entry 63's lower bound when that entry is locked with pmp63cfg.A=TOR. Without Smepmp, locking persists until hart reset. With Smepmp MML=1, L changes permission meaning, but the L=1 M-mode-only or locked Shared-Region rules it defines remain locked unless mseccfg.RLB=1 temporarily bypasses locking.
  • - pmpaddr62 is WARL; read it back after writing and interpret the masked value using the current pmp62cfg.A and grain.
  • - With pmp62cfg.A=TOR, entry 62 matches pmpaddr61 <= y < pmpaddr62; if the lower bound is not less than the upper bound, it matches no addresses. NA4 is not selectable when G>=1.

Put It Back Into A Real Flow

1

Read pmp62cfg.A to determine whether entry 62 uses OFF, TOR, NA4, or NAPOT.

2

Write pmpaddr62 for the selected mode; TOR also requires lower bound pmpaddr61, while NAPOT encodes range size in low bits.

3

Read back pmpaddr62 and the corresponding pmpcfg CSR to confirm the effective WARL/grain encoding; set pmp62cfg.L only after final verification.

FAQ

Where do pmpaddr62's TOR bounds come from?

With pmp62cfg.A=TOR, pmpaddr61 supplies the lower bound and pmpaddr62 the upper bound, so entry 62 matches the half-open range pmpaddr61 <= y < pmpaddr62; it matches no addresses when the lower bound is not less than the upper bound.

Why can pmpaddr62 read back differently from the written value?

pmpaddr62 is WARL, and platform grain plus pmp62cfg.A[1] masks low-bit readback: NAPOT can read ones while OFF/TOR reads zeros. Changing A[1] does not alter the underlying stored value.