CSR Bit Fields

RISC-V pmpcfg5 CSR Register

Address 0x3A5Privilege MachineAccess RW / RV32 only / 32-bitMachine physical memory protection CSRs

pmpcfg5 is an RV32-only physical memory protection configuration CSR; odd-numbered pmpcfg CSRs are illegal on RV64.

Field Map

Understand pmpcfg5 By Bit Fields

24 key fields
7

pmp20cfg.L

RW

Lock bit for PMP entry 20.

pmp20cfg.L (bit 7) — Lock bit for PMP entry 20.

What This Field Controls

  • - Lock bit for PMP entry 20.

Common Values

pmp20cfg.L
0Unlocked

PMP entry 20 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr20 may still be locked by a later locked TOR entry.

1Locked

PMP entry 20 is locked; writes to pmp20cfg and pmpaddr20 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr19 is also locked.

Open Official Manual
6:5

pmp20cfg.reserved

RO

Reserved bits for PMP entry 20; writes follow WARL/reserved-bit rules.

pmp20cfg.reserved (bits 6:5) — Reserved bits for PMP entry 20; writes follow WARL/reserved-bit rules.

What This Field Controls

  • - Reserved bits for PMP entry 20; writes follow WARL/reserved-bit rules.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Open Official Manual
4:3

pmp20cfg.A

RW

Address-matching mode for PMP entry 20.

pmp20cfg.A (bits 4:3) — Address-matching mode for PMP entry 20.

What This Field Controls

  • - Address-matching mode for PMP entry 20.

Common Values

pmp20cfg.A
0OFF

PMP entry 20 is disabled and matches no addresses.

1TOR

PMP entry 20 uses top-of-range matching; the upper bound comes from pmpaddr20, and the lower bound comes from pmpaddr19.

2NA4

PMP entry 20 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 20 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr20.

Open Official Manual
2

pmp20cfg.X

RW

Execute permission for PMP entry 20.

pmp20cfg.X (bit 2) — Execute permission for PMP entry 20.

What This Field Controls

  • - Execute permission for PMP entry 20.

Common Values

pmp20cfg.X
0Execute denied

PMP entry 20 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

1Execute permitted

PMP entry 20 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

Open Official Manual
1

pmp20cfg.W

RW

Write permission for PMP entry 20.

pmp20cfg.W (bit 1) — Write permission for PMP entry 20.

What This Field Controls

  • - Write permission for PMP entry 20.

Common Values

pmp20cfg.W
0Write denied

PMP entry 20 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

1Write permitted (requires R=1)

PMP entry 20 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

Open Official Manual
0

pmp20cfg.R

RW

Read permission for PMP entry 20.

pmp20cfg.R (bit 0) — Read permission for PMP entry 20.

What This Field Controls

  • - Read permission for PMP entry 20.

Common Values

pmp20cfg.R
0Read denied

PMP entry 20 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

1Read permitted

PMP entry 20 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

Open Official Manual
15

pmp21cfg.L

RW

Lock bit for PMP entry 21.

pmp21cfg.L (bit 15) — Lock bit for PMP entry 21.

What This Field Controls

  • - Lock bit for PMP entry 21.

Common Values

pmp21cfg.L
0Unlocked

PMP entry 21 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr21 may still be locked by a later locked TOR entry.

1Locked

PMP entry 21 is locked; writes to pmp21cfg and pmpaddr21 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr20 is also locked.

Open Official Manual
14:13

pmp21cfg.reserved

RO

Reserved bits for PMP entry 21; writes follow WARL/reserved-bit rules.

pmp21cfg.reserved (bits 14:13) — Reserved bits for PMP entry 21; writes follow WARL/reserved-bit rules.

What This Field Controls

  • - Reserved bits for PMP entry 21; writes follow WARL/reserved-bit rules.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Open Official Manual
12:11

pmp21cfg.A

RW

Address-matching mode for PMP entry 21.

pmp21cfg.A (bits 12:11) — Address-matching mode for PMP entry 21.

What This Field Controls

  • - Address-matching mode for PMP entry 21.

Common Values

pmp21cfg.A
0OFF

PMP entry 21 is disabled and matches no addresses.

1TOR

PMP entry 21 uses top-of-range matching; the upper bound comes from pmpaddr21, and the lower bound comes from pmpaddr20.

2NA4

PMP entry 21 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 21 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr21.

Open Official Manual
10

pmp21cfg.X

RW

Execute permission for PMP entry 21.

pmp21cfg.X (bit 10) — Execute permission for PMP entry 21.

What This Field Controls

  • - Execute permission for PMP entry 21.

Common Values

pmp21cfg.X
0Execute denied

PMP entry 21 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

1Execute permitted

PMP entry 21 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

Open Official Manual
9

pmp21cfg.W

RW

Write permission for PMP entry 21.

pmp21cfg.W (bit 9) — Write permission for PMP entry 21.

What This Field Controls

  • - Write permission for PMP entry 21.

Common Values

pmp21cfg.W
0Write denied

PMP entry 21 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

1Write permitted (requires R=1)

PMP entry 21 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

Open Official Manual
8

pmp21cfg.R

RW

Read permission for PMP entry 21.

pmp21cfg.R (bit 8) — Read permission for PMP entry 21.

What This Field Controls

  • - Read permission for PMP entry 21.

Common Values

pmp21cfg.R
0Read denied

PMP entry 21 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

1Read permitted

PMP entry 21 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

Open Official Manual
23

pmp22cfg.L

RW

Lock bit for PMP entry 22.

pmp22cfg.L (bit 23) — Lock bit for PMP entry 22.

What This Field Controls

  • - Lock bit for PMP entry 22.

Common Values

pmp22cfg.L
0Unlocked

PMP entry 22 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr22 may still be locked by a later locked TOR entry.

1Locked

PMP entry 22 is locked; writes to pmp22cfg and pmpaddr22 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr21 is also locked.

Open Official Manual
22:21

pmp22cfg.reserved

RO

Reserved bits for PMP entry 22; writes follow WARL/reserved-bit rules.

pmp22cfg.reserved (bits 22:21) — Reserved bits for PMP entry 22; writes follow WARL/reserved-bit rules.

What This Field Controls

  • - Reserved bits for PMP entry 22; writes follow WARL/reserved-bit rules.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Open Official Manual
20:19

pmp22cfg.A

RW

Address-matching mode for PMP entry 22.

pmp22cfg.A (bits 20:19) — Address-matching mode for PMP entry 22.

What This Field Controls

  • - Address-matching mode for PMP entry 22.

Common Values

pmp22cfg.A
0OFF

PMP entry 22 is disabled and matches no addresses.

1TOR

PMP entry 22 uses top-of-range matching; the upper bound comes from pmpaddr22, and the lower bound comes from pmpaddr21.

2NA4

PMP entry 22 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 22 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr22.

Open Official Manual
18

pmp22cfg.X

RW

Execute permission for PMP entry 22.

pmp22cfg.X (bit 18) — Execute permission for PMP entry 22.

What This Field Controls

  • - Execute permission for PMP entry 22.

Common Values

pmp22cfg.X
0Execute denied

PMP entry 22 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

1Execute permitted

PMP entry 22 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

Open Official Manual
17

pmp22cfg.W

RW

Write permission for PMP entry 22.

pmp22cfg.W (bit 17) — Write permission for PMP entry 22.

What This Field Controls

  • - Write permission for PMP entry 22.

Common Values

pmp22cfg.W
0Write denied

PMP entry 22 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

1Write permitted (requires R=1)

PMP entry 22 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

Open Official Manual
16

pmp22cfg.R

RW

Read permission for PMP entry 22.

pmp22cfg.R (bit 16) — Read permission for PMP entry 22.

What This Field Controls

  • - Read permission for PMP entry 22.

Common Values

pmp22cfg.R
0Read denied

PMP entry 22 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

1Read permitted

PMP entry 22 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

Open Official Manual
31

pmp23cfg.L

RW

Lock bit for PMP entry 23.

pmp23cfg.L (bit 31) — Lock bit for PMP entry 23.

What This Field Controls

  • - Lock bit for PMP entry 23.

Common Values

pmp23cfg.L
0Unlocked

PMP entry 23 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr23 may still be locked by a later locked TOR entry.

1Locked

PMP entry 23 is locked; writes to pmp23cfg and pmpaddr23 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr22 is also locked.

Open Official Manual
30:29

pmp23cfg.reserved

RO

Reserved bits for PMP entry 23; writes follow WARL/reserved-bit rules.

pmp23cfg.reserved (bits 30:29) — Reserved bits for PMP entry 23; writes follow WARL/reserved-bit rules.

What This Field Controls

  • - Reserved bits for PMP entry 23; writes follow WARL/reserved-bit rules.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Open Official Manual
28:27

pmp23cfg.A

RW

Address-matching mode for PMP entry 23.

pmp23cfg.A (bits 28:27) — Address-matching mode for PMP entry 23.

What This Field Controls

  • - Address-matching mode for PMP entry 23.

Common Values

pmp23cfg.A
0OFF

PMP entry 23 is disabled and matches no addresses.

1TOR

PMP entry 23 uses top-of-range matching; the upper bound comes from pmpaddr23, and the lower bound comes from pmpaddr22.

2NA4

PMP entry 23 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 23 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr23.

Open Official Manual
26

pmp23cfg.X

RW

Execute permission for PMP entry 23.

pmp23cfg.X (bit 26) — Execute permission for PMP entry 23.

What This Field Controls

  • - Execute permission for PMP entry 23.

Common Values

pmp23cfg.X
0Execute denied

PMP entry 23 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

1Execute permitted

PMP entry 23 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

Open Official Manual
25

pmp23cfg.W

RW

Write permission for PMP entry 23.

pmp23cfg.W (bit 25) — Write permission for PMP entry 23.

What This Field Controls

  • - Write permission for PMP entry 23.

Common Values

pmp23cfg.W
0Write denied

PMP entry 23 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

1Write permitted (requires R=1)

PMP entry 23 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

Open Official Manual
24

pmp23cfg.R

RW

Read permission for PMP entry 23.

pmp23cfg.R (bit 24) — Read permission for PMP entry 23.

What This Field Controls

  • - Read permission for PMP entry 23.

Common Values

pmp23cfg.R
0Read denied

PMP entry 23 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

1Read permitted

PMP entry 23 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

Open Official Manual

What To Check First When Reading This CSR

  • - First confirm that the current hart implements pmpcfg5; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
  • - Use address 0x3A5 and the lowest access privilege (Machine) to decide whether software may read it directly.
  • - Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

  • - Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
  • - Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.

Put It Back Into A Real Flow

1

During initialization or the relevant privileged flow, software reads pmpcfg5 to observe the current state.

2

Modify only the target fields while preserving all other bits.

3

Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.