RISC-V pmpcfg5 CSR Register

PMP entry 20 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr20 may still be locked by a later locked TOR entry.

PMP entry 20 is locked; writes to pmp20cfg and pmpaddr20 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr19 is also locked.

PMP entry 20 is disabled and matches no addresses.

PMP entry 20 uses top-of-range matching; the upper bound comes from pmpaddr20, and the lower bound comes from pmpaddr19.

PMP entry 20 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 20 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr20.

PMP entry 20 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 20 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 20 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 20 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 20 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 20 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 21 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr21 may still be locked by a later locked TOR entry.

PMP entry 21 is locked; writes to pmp21cfg and pmpaddr21 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr20 is also locked.

PMP entry 21 is disabled and matches no addresses.

PMP entry 21 uses top-of-range matching; the upper bound comes from pmpaddr21, and the lower bound comes from pmpaddr20.

PMP entry 21 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 21 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr21.

PMP entry 21 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 21 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 21 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 21 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 21 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 21 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 22 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr22 may still be locked by a later locked TOR entry.

PMP entry 22 is locked; writes to pmp22cfg and pmpaddr22 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr21 is also locked.

PMP entry 22 is disabled and matches no addresses.

PMP entry 22 uses top-of-range matching; the upper bound comes from pmpaddr22, and the lower bound comes from pmpaddr21.

PMP entry 22 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 22 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr22.

PMP entry 22 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 22 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 22 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 22 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 22 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 22 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 23 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr23 may still be locked by a later locked TOR entry.

PMP entry 23 is locked; writes to pmp23cfg and pmpaddr23 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr22 is also locked.

PMP entry 23 is disabled and matches no addresses.

PMP entry 23 uses top-of-range matching; the upper bound comes from pmpaddr23, and the lower bound comes from pmpaddr22.

PMP entry 23 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 23 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr23.

PMP entry 23 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 23 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 23 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 23 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 23 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 23 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.