RISC-V pmpcfg6 CSR Register

PMP entry 24 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr24 may still be locked by a later locked TOR entry.

PMP entry 24 is locked; writes to pmp24cfg and pmpaddr24 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr23 is also locked.

PMP entry 24 is disabled and matches no addresses.

PMP entry 24 uses top-of-range matching; the upper bound comes from pmpaddr24, and the lower bound comes from pmpaddr23.

PMP entry 24 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 24 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr24.

PMP entry 24 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 24 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 24 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 24 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 24 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 24 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 25 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr25 may still be locked by a later locked TOR entry.

PMP entry 25 is locked; writes to pmp25cfg and pmpaddr25 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr24 is also locked.

PMP entry 25 is disabled and matches no addresses.

PMP entry 25 uses top-of-range matching; the upper bound comes from pmpaddr25, and the lower bound comes from pmpaddr24.

PMP entry 25 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 25 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr25.

PMP entry 25 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 25 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 25 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 25 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 25 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 25 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 26 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr26 may still be locked by a later locked TOR entry.

PMP entry 26 is locked; writes to pmp26cfg and pmpaddr26 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr25 is also locked.

PMP entry 26 is disabled and matches no addresses.

PMP entry 26 uses top-of-range matching; the upper bound comes from pmpaddr26, and the lower bound comes from pmpaddr25.

PMP entry 26 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 26 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr26.

PMP entry 26 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 26 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 26 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 26 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 26 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 26 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 27 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr27 may still be locked by a later locked TOR entry.

PMP entry 27 is locked; writes to pmp27cfg and pmpaddr27 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr26 is also locked.

PMP entry 27 is disabled and matches no addresses.

PMP entry 27 uses top-of-range matching; the upper bound comes from pmpaddr27, and the lower bound comes from pmpaddr26.

PMP entry 27 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 27 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr27.

PMP entry 27 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 27 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 27 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 27 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 27 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 27 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 28 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr28 may still be locked by a later locked TOR entry.

PMP entry 28 is locked; writes to pmp28cfg and pmpaddr28 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr27 is also locked.

PMP entry 28 is disabled and matches no addresses.

PMP entry 28 uses top-of-range matching; the upper bound comes from pmpaddr28, and the lower bound comes from pmpaddr27.

PMP entry 28 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 28 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr28.

PMP entry 28 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 28 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 28 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 28 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 28 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 28 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 29 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr29 may still be locked by a later locked TOR entry.

PMP entry 29 is locked; writes to pmp29cfg and pmpaddr29 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr28 is also locked.

PMP entry 29 is disabled and matches no addresses.

PMP entry 29 uses top-of-range matching; the upper bound comes from pmpaddr29, and the lower bound comes from pmpaddr28.

PMP entry 29 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 29 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr29.

PMP entry 29 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 29 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 29 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 29 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 29 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 29 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 30 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr30 may still be locked by a later locked TOR entry.

PMP entry 30 is locked; writes to pmp30cfg and pmpaddr30 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr29 is also locked.

PMP entry 30 is disabled and matches no addresses.

PMP entry 30 uses top-of-range matching; the upper bound comes from pmpaddr30, and the lower bound comes from pmpaddr29.

PMP entry 30 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 30 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr30.

PMP entry 30 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 30 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 30 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 30 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 30 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 30 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 31 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr31 may still be locked by a later locked TOR entry.

PMP entry 31 is locked; writes to pmp31cfg and pmpaddr31 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr30 is also locked.

PMP entry 31 is disabled and matches no addresses.

PMP entry 31 uses top-of-range matching; the upper bound comes from pmpaddr31, and the lower bound comes from pmpaddr30.

PMP entry 31 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 31 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr31.

PMP entry 31 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 31 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 31 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 31 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 31 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 31 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.