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CSR Bit Fields

RISC-V pmpcfg6 CSR Register

Address 0x3A6Privilege MachineAccess Machine RW (all fields WARL/may be RO0) / MXLEN: 32 bits on RV32; 64 bits on RV64Machine physical memory protection CSRs

pmpcfg6 (0x3A6) is a machine PMP configuration CSR packing pmp24cfg-pmp27cfg on RV32 and pmp24cfg-pmp31cfg on RV64.

Related Search Terms
pmpcfg6 CSRpmpcfg6 0x3A6PMP R W XPMP A fieldPMP L bitPMP entries 24-31
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
pmp31cfg.L63WARL/may be RO0pmp24cfg.R0Collective WARL (R/W/X)
Field Map

Understand pmpcfg6 By Bit Fields

48 key fields
7

pmp24cfg.L

WARL/may be RO0

Lock bit for PMP entry 24. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp24cfg.L (bit 7) — Lock bit for PMP entry 24. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 24. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp24cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
6:5

pmp24cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp24cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp24cfg.reserved (bits 6:5) — Bits 6:5 of pmp24cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp24cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
4:3

pmp24cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 24. This field is WARL and may be implemented as read-only zero.

pmp24cfg.A (bits 4:3) — Address-matching mode for PMP entry 24. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 24. This field is WARL and may be implemented as read-only zero.

Common Values

pmp24cfg.A
0OFF

PMP entry 24 is disabled and matches no addresses.

1TOR

PMP entry 24 uses top-of-range matching; the upper bound comes from pmpaddr24, and the lower bound comes from pmpaddr23.

2NA4

PMP entry 24 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 24 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr24.

↗Open Official Manual
2

pmp24cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 24; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp24cfg.X (bit 2) — X bit for PMP entry 24; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 24; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp24cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
1

pmp24cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 24; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp24cfg.W (bit 1) — W bit for PMP entry 24; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 24; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp24cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
0

pmp24cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 24; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp24cfg.R (bit 0) — R bit for PMP entry 24; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 24; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp24cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
15

pmp25cfg.L

WARL/may be RO0

Lock bit for PMP entry 25. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp25cfg.L (bit 15) — Lock bit for PMP entry 25. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 25. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp25cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
14:13

pmp25cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp25cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp25cfg.reserved (bits 14:13) — Bits 6:5 of pmp25cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp25cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
12:11

pmp25cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 25. This field is WARL and may be implemented as read-only zero.

pmp25cfg.A (bits 12:11) — Address-matching mode for PMP entry 25. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 25. This field is WARL and may be implemented as read-only zero.

Common Values

pmp25cfg.A
0OFF

PMP entry 25 is disabled and matches no addresses.

1TOR

PMP entry 25 uses top-of-range matching; the upper bound comes from pmpaddr25, and the lower bound comes from pmpaddr24.

2NA4

PMP entry 25 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 25 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr25.

↗Open Official Manual
10

pmp25cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 25; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp25cfg.X (bit 10) — X bit for PMP entry 25; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 25; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp25cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
9

pmp25cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 25; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp25cfg.W (bit 9) — W bit for PMP entry 25; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 25; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp25cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
8

pmp25cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 25; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp25cfg.R (bit 8) — R bit for PMP entry 25; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 25; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp25cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
23

pmp26cfg.L

WARL/may be RO0

Lock bit for PMP entry 26. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp26cfg.L (bit 23) — Lock bit for PMP entry 26. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 26. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp26cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
22:21

pmp26cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp26cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp26cfg.reserved (bits 22:21) — Bits 6:5 of pmp26cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp26cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
20:19

pmp26cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 26. This field is WARL and may be implemented as read-only zero.

pmp26cfg.A (bits 20:19) — Address-matching mode for PMP entry 26. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 26. This field is WARL and may be implemented as read-only zero.

Common Values

pmp26cfg.A
0OFF

PMP entry 26 is disabled and matches no addresses.

1TOR

PMP entry 26 uses top-of-range matching; the upper bound comes from pmpaddr26, and the lower bound comes from pmpaddr25.

2NA4

PMP entry 26 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 26 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr26.

↗Open Official Manual
18

pmp26cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 26; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp26cfg.X (bit 18) — X bit for PMP entry 26; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 26; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp26cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
17

pmp26cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 26; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp26cfg.W (bit 17) — W bit for PMP entry 26; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 26; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp26cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
16

pmp26cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 26; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp26cfg.R (bit 16) — R bit for PMP entry 26; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 26; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp26cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
31

pmp27cfg.L

WARL/may be RO0

Lock bit for PMP entry 27. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp27cfg.L (bit 31) — Lock bit for PMP entry 27. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 27. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp27cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
30:29

pmp27cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp27cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp27cfg.reserved (bits 30:29) — Bits 6:5 of pmp27cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp27cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
28:27

pmp27cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 27. This field is WARL and may be implemented as read-only zero.

pmp27cfg.A (bits 28:27) — Address-matching mode for PMP entry 27. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 27. This field is WARL and may be implemented as read-only zero.

Common Values

pmp27cfg.A
0OFF

PMP entry 27 is disabled and matches no addresses.

1TOR

PMP entry 27 uses top-of-range matching; the upper bound comes from pmpaddr27, and the lower bound comes from pmpaddr26.

2NA4

PMP entry 27 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 27 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr27.

↗Open Official Manual
26

pmp27cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 27; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp27cfg.X (bit 26) — X bit for PMP entry 27; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 27; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp27cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
25

pmp27cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 27; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp27cfg.W (bit 25) — W bit for PMP entry 27; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 27; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp27cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
24

pmp27cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 27; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp27cfg.R (bit 24) — R bit for PMP entry 27; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 27; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp27cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
39

pmp28cfg.L

WARL/may be RO0

Lock bit for PMP entry 28. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp28cfg.L (bit 39) — Lock bit for PMP entry 28. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 28. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp28cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
38:37

pmp28cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp28cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp28cfg.reserved (bits 38:37) — Bits 6:5 of pmp28cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp28cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
36:35

pmp28cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 28. This field is WARL and may be implemented as read-only zero.

pmp28cfg.A (bits 36:35) — Address-matching mode for PMP entry 28. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 28. This field is WARL and may be implemented as read-only zero.

Common Values

pmp28cfg.A
0OFF

PMP entry 28 is disabled and matches no addresses.

1TOR

PMP entry 28 uses top-of-range matching; the upper bound comes from pmpaddr28, and the lower bound comes from pmpaddr27.

2NA4

PMP entry 28 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 28 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr28.

↗Open Official Manual
34

pmp28cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 28; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp28cfg.X (bit 34) — X bit for PMP entry 28; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 28; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp28cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
33

pmp28cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 28; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp28cfg.W (bit 33) — W bit for PMP entry 28; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 28; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp28cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
32

pmp28cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 28; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp28cfg.R (bit 32) — R bit for PMP entry 28; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 28; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp28cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
47

pmp29cfg.L

WARL/may be RO0

Lock bit for PMP entry 29. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp29cfg.L (bit 47) — Lock bit for PMP entry 29. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 29. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp29cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
46:45

pmp29cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp29cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp29cfg.reserved (bits 46:45) — Bits 6:5 of pmp29cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp29cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
44:43

pmp29cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 29. This field is WARL and may be implemented as read-only zero.

pmp29cfg.A (bits 44:43) — Address-matching mode for PMP entry 29. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 29. This field is WARL and may be implemented as read-only zero.

Common Values

pmp29cfg.A
0OFF

PMP entry 29 is disabled and matches no addresses.

1TOR

PMP entry 29 uses top-of-range matching; the upper bound comes from pmpaddr29, and the lower bound comes from pmpaddr28.

2NA4

PMP entry 29 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 29 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr29.

↗Open Official Manual
42

pmp29cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 29; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp29cfg.X (bit 42) — X bit for PMP entry 29; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 29; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp29cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
41

pmp29cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 29; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp29cfg.W (bit 41) — W bit for PMP entry 29; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 29; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp29cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
40

pmp29cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 29; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp29cfg.R (bit 40) — R bit for PMP entry 29; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 29; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp29cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
55

pmp30cfg.L

WARL/may be RO0

Lock bit for PMP entry 30. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp30cfg.L (bit 55) — Lock bit for PMP entry 30. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 30. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp30cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
54:53

pmp30cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp30cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp30cfg.reserved (bits 54:53) — Bits 6:5 of pmp30cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp30cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
52:51

pmp30cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 30. This field is WARL and may be implemented as read-only zero.

pmp30cfg.A (bits 52:51) — Address-matching mode for PMP entry 30. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 30. This field is WARL and may be implemented as read-only zero.

Common Values

pmp30cfg.A
0OFF

PMP entry 30 is disabled and matches no addresses.

1TOR

PMP entry 30 uses top-of-range matching; the upper bound comes from pmpaddr30, and the lower bound comes from pmpaddr29.

2NA4

PMP entry 30 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 30 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr30.

↗Open Official Manual
50

pmp30cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 30; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp30cfg.X (bit 50) — X bit for PMP entry 30; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 30; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp30cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
49

pmp30cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 30; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp30cfg.W (bit 49) — W bit for PMP entry 30; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 30; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp30cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
48

pmp30cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 30; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp30cfg.R (bit 48) — R bit for PMP entry 30; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 30; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp30cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
63

pmp31cfg.L

WARL/may be RO0

Lock bit for PMP entry 31. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp31cfg.L (bit 63) — Lock bit for PMP entry 31. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 31. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp31cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
62:61

pmp31cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp31cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp31cfg.reserved (bits 62:61) — Bits 6:5 of pmp31cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp31cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
60:59

pmp31cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 31. This field is WARL and may be implemented as read-only zero.

pmp31cfg.A (bits 60:59) — Address-matching mode for PMP entry 31. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 31. This field is WARL and may be implemented as read-only zero.

Common Values

pmp31cfg.A
0OFF

PMP entry 31 is disabled and matches no addresses.

1TOR

PMP entry 31 uses top-of-range matching; the upper bound comes from pmpaddr31, and the lower bound comes from pmpaddr30.

2NA4

PMP entry 31 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 31 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr31.

↗Open Official Manual
58

pmp31cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 31; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp31cfg.X (bit 58) — X bit for PMP entry 31; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 31; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp31cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
57

pmp31cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 31; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp31cfg.W (bit 57) — W bit for PMP entry 31; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 31; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp31cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
56

pmp31cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 31; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp31cfg.R (bit 56) — R bit for PMP entry 31; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 31; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp31cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
Official Basis & Search Notes

pmpcfg6 packs four 8-bit PMP configurations on RV32 and eight on RV64; each contains L, A, X, W, R, and two reserved zero bits.

The Machine ISA Physical Memory Protection CSRs subsection defines the address, MXLEN packing, M-mode-only access, and WARL/RO0 behavior.
A encodes OFF, TOR, NA4, or NAPOT; platform grain may make NA4 unselectable.
Base PMP and Smepmp with MML=1 interpret L/R/W/X differently, so field values must be read with mseccfg state.
RISC-V ISA Manual 2026-07-09 release - Machine ISA PMPRISC-V Privileged Architecture - Physical Memory ProtectionRISC-V Privileged Architecture - Smepmp Physical Memory Protection Rules

What To Check First When Reading This CSR

  • - pmpcfg6 contains entries 24-27 on RV32 and entries 24-31 in the same CSR on RV64.
  • - PMP is optional; implementations may provide 0, 16, or 64 entries, and every PMP CSR field is WARL and may be read-only zero.
  • - PMP CSRs are accessible only to M-mode.
  • - The M-mode permission bypass described on this page applies only when effective privilege is M; mstatus.MPRV can make an M-mode data access undergo PMP checks with effective S/U privilege.
  • - At reset, writable PMP A and L fields become 0 unless the platform mandates different values for some PMP registers; other PMP field reset values are unspecified, but no WARL field contains an illegal value.

Risk Checks Before Writing

  • - R/W/X form one collective WARL field. In base PMP (mseccfg.MML=0), combinations with R=0 and W=1 are reserved; Smepmp collectively reinterprets L/R/W/X when MML=1.
  • - L=1 locks pmpNcfg and pmpaddrN until hart reset; with A=TOR it also locks the preceding pmpaddr. Smepmp mseccfg.RLB can bypass locking rules.
  • - Read back WARL fields after writing; do not assume an unimplemented permission or matching mode is accepted.

Put It Back Into A Real Flow

1

Choose OFF, TOR, NA4, or NAPOT in A and encode the range in pmpaddrN (and the preceding address register for TOR).

2

Interpret and write the collective WARL L/R/W/X encoding according to the current mseccfg.MML state.

3

Read back pmpcfg and pmpaddr to confirm the implemented WARL values; set L only after finalizing the configuration.

FAQ

Does pmpcfg6 contain the same number of entries on RV32 and RV64?

No. RV32 pmpcfg6 packs pmp24cfg-pmp27cfg, while RV64 pmpcfg6 packs pmp24cfg-pmp31cfg.