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CSR Bit Fields

RISC-V sstateen0 CSR Register

Address 0x10CPrivilege SupervisorAccess RW / XLENSupervisor environment-configuration and state-enable CSRs

sstateen0 at 0x10C is an Ssstateen Supervisor state-enable CSR controlling U/VU-mode access to corresponding extension state.

Related Search Terms
sstateen0 CSRsstateen0 0x10CSsstateenSupervisor state enablesstateen0 WARLU/VU state access
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
RO063:32RO0WPRI31:3WPRI/undefined reserved bits read zeroJVT2WARL/may be RO0FCSR1WARL/may be RO0SE00WARL/may be RO0
Field Map

Understand sstateen0 By Bit Fields

5 key fields
XLEN-1:32

RO0

RO0

Supervisor-level `sstateen` currently has no high-half CSR; on RV64 these upper bits read as zero.

RO0 (bits XLEN-1:32) — Supervisor-level `sstateen` currently has no high-half CSR; on RV64 these upper bits read as zero.

What This Field Controls

  • - Supervisor-level `sstateen` currently has no high-half CSR; on RV64 these upper bits read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
31:3

WPRI

WPRI/undefined reserved bits read zero

Bits 3 through 31 currently have no defined user-level state control in `sstateen0`; under stateen rules, reserved bits not yet defined read as zero and should be preserved when writing other fields.

WPRI (bits 31:3) — Bits 3 through 31 currently have no defined user-level state control in `sstateen0`; under stateen rules, reserved bits not yet defined read as zero and should be preserved when writing other fields.

What This Field Controls

  • - Bits 3 through 31 currently have no defined user-level state control in `sstateen0`; under stateen rules, reserved bits not yet defined read as zero and should be preserved when writing other fields.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
2

JVT

WARL/may be RO0

Controls U/VU-mode access to the `jvt` CSR provided by the Zcmt extension. If the corresponding state is not implemented, or an upper-level stateen bit is zero, this bit reads as zero.

JVT (bit 2) — Controls U/VU-mode access to the `jvt` CSR provided by the Zcmt extension. If the corresponding state is not implemented, or an upper-level stateen bit is zero, this bit reads as zero.

What This Field Controls

  • - Controls U/VU-mode access to the `jvt` CSR provided by the Zcmt extension. If the corresponding state is not implemented, or an upper-level stateen bit is zero, this bit reads as zero.

Common Values

0Disabled

Denies U/VU-mode access to the controlled jvt state.

1Enabled

Allows U/VU-mode access to the controlled jvt state.

↗Open Official Manual
1

FCSR

WARL/may be RO0

Controls access to `fcsr` for Zfinx and related extensions when floating-point instructions operate on x registers; when `misa.F=1`, this bit is read-only zero.

FCSR (bit 1) — Controls access to `fcsr` for Zfinx and related extensions when floating-point instructions operate on x registers; when `misa.F=1`, this bit is read-only zero.

What This Field Controls

  • - Controls access to `fcsr` for Zfinx and related extensions when floating-point instructions operate on x registers; when `misa.F=1`, this bit is read-only zero.

Common Values

0Disabled

Denies U/VU-mode access to the controlled fcsr state; floating-point instructions may therefore trap under the specified conditions.

1Enabled

Allows U/VU-mode access to the controlled fcsr state.

↗Open Official Manual
0

SE0

WARL/may be RO0

Controls U/VU-mode access to any and all custom state; the bit itself is a standard CSR field, not custom state.

SE0 (bit 0) — Controls U/VU-mode access to any and all custom state; the bit itself is a standard CSR field, not custom state.

What This Field Controls

  • - Controls U/VU-mode access to any and all custom state; the bit itself is a standard CSR field, not custom state.

Common Values

0Disabled

Denies U/VU-mode access to controlled custom state.

1Enabled

Allows U/VU-mode access to controlled custom state.

↗Open Official Manual
Official Basis & Search Notes

sstateen0 is a supervisor-level state-enable CSR. It controls user-level access to protected extension state bit by bit; standard-defined bits are WARL, while unimplemented state and undefined reserved bits read zero.

The official Smstateen/Ssstateen chapter defines `sstateen0-3` as supervisor-level CSRs and currently provides no supervisor-level high-half CSRs.
`sstateen` bits control U/VU-mode access to extension state, not same-level S-mode access.
Each standard-defined bit is WARL; unimplemented state and undefined reserved bits read as zero.
RISC-V Privileged Architecture Manual: CSR ListingRISC-V Privileged Architecture Manual: Smstateen/Ssstateen

What To Check First When Reading This CSR

  • - Supervisor-level `sstateen` CSRs control U/VU-mode access, not access by S-mode itself; the upper 32 bits read as zero on RV64.
  • - Each standard-defined bit is WARL; bits for unimplemented state and undefined reserved bits read as zero.
  • - If the matching `mstateen` bit is zero, the same bit reads as zero in `sstateen`; VS-mode access is also affected by the matching `hstateen` bit.

Risk Checks Before Writing

  • - Do not infer extension functions from undefined bit positions; preserve unchanged bits and read back to confirm WARL-accepted values.
  • - When an OS is first entered, software should ensure writable `sstateen` bits are initialized to zero before enabling user-level access as needed.

Put It Back Into A Real Flow

1

Confirm whether upper-level `mstateen`/`hstateen` permits access to the matching `sstateen` CSR and corresponding state.

2

S-mode sets only the extension-state bits it is prepared to expose to U/VU mode.

3

Execute the controlled state access at user level; denied access is expected to trap as specified.

FAQ

Can sstateen0 be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records sstateen0 as Supervisor. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing sstateen0?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.