RISC-V sstateen3 CSR Register

Address 0x10FPrivilege SupervisorAccess RW / XLENSupervisor environment-configuration and state-enable CSRs

sstateen3 (0x10F) is the Supervisor State Enable 3 CSR defined by Ssstateen/Smstateen; it follows the sstateen framework in which bits with defined purposes control U-mode or VU-mode access to corresponding extension state.

Related Search Terms

sstateen3 CSR sstateen3 0x10F Supervisor State Enable 3 sstateen3 WARL sstateen3 upper bits zero RISC-V sstateen3

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

RESERVED63:32RO0 STATEEN31:0WARL/RO0

Field Map

Understand sstateen3 By Bit Fields

2 key fields

31:0

STATEEN

WARL/RO0

sstateen CSR bits are allocated from the least-significant end; each bit with a defined purpose controls U-mode or VU-mode access to corresponding extension state. Each standard-defined stateen bit is WARL, but bits for unimplemented controlled state and reserved bits not yet defined read as zero. If the matching mstateen3 bit is zero, or in VS-mode the matching hstateen3 bit is zero, the same sstateen3 bit appears read-only zero.

STATEEN (bits 31:0) — sstateen CSR bits are allocated from the least-significant end; each bit with a defined purpose controls U-mode or VU-mode access to corresponding extension state. Each standard-defined stateen bit is WARL, but bits for unimplemented controlled state and reserved bits not yet defined read as zero. If the matching mstateen3 bit is zero, or in VS-mode the matching hstateen3 bit is zero, the same sstateen3 bit appears read-only zero.

What This Field Controls

- sstateen CSR bits are allocated from the least-significant end; each bit with a defined purpose controls U-mode or VU-mode access to corresponding extension state. Each standard-defined stateen bit is WARL, but bits for unimplemented controlled state and reserved bits not yet defined read as zero. If the matching mstateen3 bit is zero, or in VS-mode the matching hstateen3 bit is zero, the same sstateen3 bit appears read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

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XLEN-1:32

RESERVED

RO0

Supervisor-level sstateen CSRs currently have no high-half CSRs; the official specification expects the upper 32 bits of these registers to always be zero.

RESERVED (bits XLEN-1:32) — Supervisor-level sstateen CSRs currently have no high-half CSRs; the official specification expects the upper 32 bits of these registers to always be zero.

What This Field Controls

- Supervisor-level sstateen CSRs currently have no high-half CSRs; the official specification expects the upper 32 bits of these registers to always be zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

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Official Basis & Search Notes

sstateen3 is the SRW Supervisor State Enable 3 CSR at 0x10F. It carries the third supervisor-level state-enable group under the general sstateen rules; only bits that are officially defined and implemented as writable have control meaning, while unimplemented state, undefined reserved bits, and upper bits read as zero.

sstateen3 address, access level, and name are checked against the official CSR table: 0x10F, SRW, Supervisor State Enable 3 Register.

sstateen bits are allocated from the least-significant end; each sstateen bit with a defined purpose controls U/VU access to corresponding extension state. The same bit in the matching mstateen CSR controls access below machine level, and VS-mode is also affected by the matching hstateen bit.

Supervisor-level sstateen CSRs currently have no high-half CSRs; the specification expects the upper 32 bits of these registers to always be zero.

RISC-V Privileged Architecture Manual v20260120, CSR table RISC-V Privileged Architecture Manual v20260120, Smstateen/Ssstateen

What To Check First When Reading This CSR

- First confirm that Ssstateen/Smstateen is implemented and that matching mstateen3 bit 63, and hstateen3 bit 63 in VS-mode, permits access to sstateen3.
- Use the official CSR table to confirm address 0x10F, SRW access, and the Supervisor State Enable 3 name.
- For the low 32 bits, interpret only officially defined stateen bits; unimplemented state, undefined reserved bits, and bits masked by upper-level stateen bits read as zero.
- The upper 32 bits are expected to always be zero; supervisor-level sstateen CSRs currently have no RV32 high-half access CSR.

Risk Checks Before Writing

- Supervisor software should initialize all writable sstateen bits to zero when an OS is first entered, then set only the bits for user-level extension state it can context-swap.
- Modify only officially defined stateen bits implemented as writable; bits for unimplemented state and undefined reserved bits read as zero, and writes should be read back to confirm the WARL-accepted value.
- Do not treat the upper 32 bits as usable control bits; the specification says the upper 32 bits of sstateen registers are expected to always be zero.

Put It Back Into A Real Flow

When a supervisor OS first runs or restores context, first confirm that upper-level mstateen3/hstateen3 controls permit access to sstateen3.

Read sstateen3 and interpret only officially defined low-32-bit stateen items to determine current U/VU extension-state access.

Set corresponding writable bits only for user-level extension state the OS can save and restore, then read back the WARL-accepted value.

FAQ

Can sstateen3 be accessed from any privilege level?

No. The official CSR table lists sstateen3 as an SRW CSR at 0x10F. S-mode access can also be controlled by matching mstateen3 bit 63, and VS-mode access can also be controlled by matching hstateen3 bit 63.

What is easiest to miss when writing sstateen3?

The easy point to miss is that only officially defined low-32-bit stateen bits implemented as writable have control meaning; unimplemented state, undefined reserved bits, bits masked by upper-level stateen controls, and upper bits read as zero.