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CSR Bit Fields

RISC-V vl CSR Register

Address 0xC20Privilege User/VectorAccess RO / XLENUser vector state CSRs

vl is the XLEN-bit read-only vector-length CSR and gives the body-element bound; active elements must also satisfy vstart <= i < vl and be mask-enabled, so vl is not generally the active element count.

Related Search Terms
vl CSRvl 0xC20vector lengthvsetvlRVV vl
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
VL63:0RO
Field Map

Understand vl By Bit Fields

1 key fields
XLEN-1:0

VL

RO

vl is the XLEN-bit read-only vector-length CSR and gives the body-element bound; active elements must also satisfy vstart <= i < vl and be mask-enabled, so vl is not generally the active element count. It can only be updated by vset{i}vl{i} instructions and fault-only-first vector-load variants.

VL (bits XLEN-1:0) — vl is the XLEN-bit read-only vector-length CSR and gives the body-element bound; active elements must also satisfy vstart <= i < vl and be mask-enabled, so vl is not generally the active element count. It can only be updated by vset{i}vl{i} instructions and fault-only-first vector-load variants.

What This Field Controls

  • - vl is the XLEN-bit read-only vector-length CSR and gives the body-element bound; active elements must also satisfy vstart <= i < vl and be mask-enabled, so vl is not generally the active element count. It can only be updated by vset{i}vl{i} instructions and fault-only-first vector-load variants.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

vl is the XLEN-bit read-only vector-length CSR and gives the body-element bound; active elements must also satisfy vstart <= i < vl and be mask-enabled, so vl is not generally the active element count.

vl is an XLEN-bit read-only CSR, updated only by vset{i}vl{i} and fault-only-first vector-load variants.
vset{i}vl{i} sets vl from AVL and vtype.
RISC-V Unprivileged ISA ManualRISC-V Privileged Architecture Manual

What To Check First When Reading This CSR

  • - Accessing a vector CSR raises an illegal-instruction exception when mstatus.VS is Off.
  • - The number of implemented vl bits depends on the implementation’s maximum vector length of the smallest supported type.

Risk Checks Before Writing

  • - vl is a read-only CSR; software cannot directly modify it with a CSR write.
  • - Use vset{i}vl{i}, or the applicable fault-only-first-load semantics, to update vl.

Put It Back Into A Real Flow

1

Use vset{i}vl{i} to set vtype and vl and receive the new vl in a general-purpose register.

2

Read vl to obtain the current vector-length setting; combine it with vstart and the mask to identify active elements.

FAQ

Which operations can update vl?

vl is read-only to CSR instructions; only vset{i}vl{i} configuration instructions and fault-only-first vector-load variants can update it.