CSR Bit Fields

RISC-V vtype CSR Register

Address 0xC21Privilege User/VectorAccess RO / XLENUser vector state CSRs

vtype at 0xC21 is a Vector type CSR: describes vector element width, LMUL, tail policy, and mask policy.

Field Map

Understand vtype By Bit Fields

6 key fields
XLEN-1

vill

RO

Illegal-vtype flag; 1 means the most recent vector configuration is unsupported.

vill (bits XLEN-1) — Illegal-vtype flag; 1 means the most recent vector configuration is unsupported.

What This Field Controls

  • - Illegal-vtype flag; 1 means the most recent vector configuration is unsupported.

Common Values

00

The current vtype configuration is valid or supported by the implementation.

11

The current vtype configuration is illegal or unsupported; the remaining vtype bits are zero and vl is set to zero.

XLEN-2:8

reserved

RO

Reserved bits; software must not depend on a fixed read value. vtype is updated by vector configuration instructions, not by CSR writes.

reserved (bits XLEN-2:8) — Reserved bits; software must not depend on a fixed read value. vtype is updated by vector configuration instructions, not by CSR writes.

What This Field Controls

  • - Reserved bits; software must not depend on a fixed read value. vtype is updated by vector configuration instructions, not by CSR writes.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

7

vma

RO

Vector mask policy, set by vector configuration instructions such as vsetvli, vsetivli, or vsetvl.

vma (bit 7) — Vector mask policy, set by vector configuration instructions such as vsetvli, vsetivli, or vsetvl.

What This Field Controls

  • - Vector mask policy, set by vector configuration instructions such as vsetvli, vsetivli, or vsetvl.

Common Values

00

Mask-undisturbed: inactive mask elements keep their old values.

11

Mask-agnostic: inactive mask elements may be overwritten with all 1s by the implementation.

6

vta

RO

Vector tail policy, set by vector configuration instructions such as vsetvli, vsetivli, or vsetvl.

vta (bit 6) — Vector tail policy, set by vector configuration instructions such as vsetvli, vsetivli, or vsetvl.

What This Field Controls

  • - Vector tail policy, set by vector configuration instructions such as vsetvli, vsetivli, or vsetvl.

Common Values

00

Tail-undisturbed: tail elements keep their old values.

11

Tail-agnostic: tail elements may be overwritten with all 1s by the implementation.

5:3

vsew

RO

Vector selected element width encoding, set by vector configuration instructions.

vsew (bits 5:3) — Vector selected element width encoding, set by vector configuration instructions.

What This Field Controls

  • - Vector selected element width encoding, set by vector configuration instructions.

Common Values

0e8

Selects SEW=8; if unsupported, vtype.vill is set.

1e16

Selects SEW=16; if unsupported, vtype.vill is set.

2e32

Selects SEW=32; if unsupported, vtype.vill is set.

3e64

Selects SEW=64; if unsupported, vtype.vill is set.

4Reserved

Reserved vsew encoding in the V specification; portable software must not write or depend on it.

5Reserved

Reserved vsew encoding in the V specification; portable software must not write or depend on it.

6Reserved

Reserved vsew encoding in the V specification; portable software must not write or depend on it.

7Reserved

Reserved vsew encoding in the V specification; portable software must not write or depend on it.

2:0

vlmul

RO

Vector register grouping multiplier encoding, set by vector configuration instructions.

vlmul (bits 2:0) — Vector register grouping multiplier encoding, set by vector configuration instructions.

What This Field Controls

  • - Vector register grouping multiplier encoding, set by vector configuration instructions.

Common Values

0m1

LMUL=1.

1m2

LMUL=2.

2m4

LMUL=4.

3m8

LMUL=8.

4Reserved

Reserved encoding for an LMUL setting below the minimum SEW/ELEN ratio; portable software must not write or depend on it.

5mf8

LMUL=1/8.

6mf4

LMUL=1/4.

7mf2

LMUL=1/2.

Official Basis & Search Notes

vtype is a RO CSR in user vector state csrs at 0xC21. Check privilege and implemented extensions before interpreting its bit fields.

vtype address, lowest access privilege, and access class are checked against the official CSR table: 0xC21, User/Vector, RO.
vtype belongs to vector-extension state; it has the corresponding software meaning only when the relevant vector extension is implemented.
This is a read-only CSR; do not write it through CSR instructions. vl/vtype are updated by vector configuration instructions such as vsetvli, vsetivli, or vsetvl.

What To Check First When Reading This CSR

  • - First confirm that the current hart implements vtype; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
  • - Use address 0xC21 and the lowest access privilege (User/Vector) to decide whether software may read it directly.
  • - Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

  • - vtype is a read-only CSR; writes raise an illegal-instruction exception or are disallowed by the implementation.

Put It Back Into A Real Flow

1

Read vtype to obtain hardware or runtime state.

2

Interpret the returned value according to the field descriptions and do not attempt to write it back.

3

If reading fails at the current privilege level, handle the illegal-instruction exception path.

FAQ

Can vtype be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records vtype as User/Vector. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when using vtype?

vtype is read-only. Treat it as an observation point, do not try to write it, and do not depend on fixed values for reserved or WPRI fields.