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CSR Bit Fields

RISC-V vtype CSR Register

Address 0xC21Privilege User/VectorAccess RO / XLENUser vector state CSRs

vtype at 0xC21 is a Vector type CSR: describes vector element width, LMUL, tail policy, and mask policy.

Related Search Terms
vtype CSRvtype 0xC21vtype SEW LMULvtype vill bitvector tail mask policyRVV vtype
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
vill63ROvlmul2:0RO
Field Map

Understand vtype By Bit Fields

6 key fields
XLEN-1

vill

RO

Illegal-vtype flag; 1 means the most recent vector configuration is unsupported.

vill (bits XLEN-1) — Illegal-vtype flag; 1 means the most recent vector configuration is unsupported.

What This Field Controls

  • - Illegal-vtype flag; 1 means the most recent vector configuration is unsupported.

Common Values

00

The current vtype configuration is valid or supported by the implementation.

11

Indicates an unsupported vtype configuration; the remaining vtype bits are zero and vector instructions that depend on vtype raise an illegal-instruction exception. When vset{i}vl{i} is given an unsupported vtype value, it also sets vl to zero.

XLEN-2:8

reserved

RO

Reserved bits: instructions that set vtype should write these bits as zero; nonzero values are reserved. Only vector configuration instructions update vtype, not CSR write instructions.

reserved (bits XLEN-2:8) — Reserved bits: instructions that set vtype should write these bits as zero; nonzero values are reserved. Only vector configuration instructions update vtype, not CSR write instructions.

What This Field Controls

  • - Reserved bits: instructions that set vtype should write these bits as zero; nonzero values are reserved. Only vector configuration instructions update vtype, not CSR write instructions.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

7

vma

RO

Vector mask policy, set by vector configuration instructions such as vsetvli, vsetivli, or vsetvl.

vma (bit 7) — Vector mask policy, set by vector configuration instructions such as vsetvli, vsetivli, or vsetvl.

What This Field Controls

  • - Vector mask policy, set by vector configuration instructions such as vsetvli, vsetivli, or vsetvl.

Common Values

00

Mask-undisturbed: inactive mask elements keep their old values.

11

Mask-agnostic: inactive elements may retain their old values or be overwritten with all 1s.

6

vta

RO

Vector tail policy, set by vector configuration instructions such as vsetvli, vsetivli, or vsetvl.

vta (bit 6) — Vector tail policy, set by vector configuration instructions such as vsetvli, vsetivli, or vsetvl.

What This Field Controls

  • - Vector tail policy, set by vector configuration instructions such as vsetvli, vsetivli, or vsetvl.

Common Values

00

Tail-undisturbed: tail elements keep their old values.

11

Tail-agnostic: tail elements may retain their old values or be overwritten with all 1s.

5:3

vsew

RO

Vector selected element width encoding, set by vector configuration instructions.

vsew (bits 5:3) — Vector selected element width encoding, set by vector configuration instructions.

What This Field Controls

  • - Vector selected element width encoding, set by vector configuration instructions.

Common Values

0e8

Selects SEW=8; if unsupported, vtype.vill is set.

1e16

Selects SEW=16; if unsupported, vtype.vill is set.

2e32

Selects SEW=32; if unsupported, vtype.vill is set.

3e64

Selects SEW=64; if unsupported, vtype.vill is set.

4Reserved

Reserved vsew encoding in the V specification; portable software must not write or depend on it.

5Reserved

Reserved vsew encoding in the V specification; portable software must not write or depend on it.

6Reserved

Reserved vsew encoding in the V specification; portable software must not write or depend on it.

7Reserved

Reserved vsew encoding in the V specification; portable software must not write or depend on it.

2:0

vlmul

RO

Vector register grouping multiplier encoding, set by vector configuration instructions.

vlmul (bits 2:0) — Vector register grouping multiplier encoding, set by vector configuration instructions.

What This Field Controls

  • - Vector register grouping multiplier encoding, set by vector configuration instructions.

Common Values

0m1

LMUL=1.

1m2

LMUL=2.

2m4

LMUL=4.

3m8

LMUL=8.

4Reserved

Reserved encoding; portable software must not write or depend on it.

5mf8

LMUL=1/8.

6mf4

LMUL=1/4.

7mf2

LMUL=1/2.

Official Basis & Search Notes

vtype is the URO vector CSR at 0xC21. It shows the current SEW, LMUL, tail policy, and mask policy, and is updated by vsetvl-class instructions.

vtype address, lowest access privilege, and access class are checked against the official CSR table: 0xC21, User/Vector, RO.
vtype belongs to vector-extension state; it has the corresponding software meaning only when the relevant vector extension is implemented.
This is a read-only CSR; do not write it through CSR instructions. vl/vtype are updated by vector configuration instructions such as vsetvli, vsetivli, or vsetvl.
RISC-V Privileged Architecture ManualRISC-V Unprivileged ISA Manual

What To Check First When Reading This CSR

  • - With the V extension, mstatus.VS=Off makes vector-CSR access raise an illegal-instruction exception; with V=1, vsstatus.VS=Off or mstatus.VS=Off does so as well.
  • - Use address 0xC21 and the lowest access privilege (User/Vector) to decide whether software may read it directly.
  • - Instructions that set vtype should write XLEN-2:8 as zero; nonzero values are reserved.

Risk Checks Before Writing

  • - vtype is read-only; do not write it with CSR write instructions. Only vsetvli, vsetivli, and vsetvl can update it.

Put It Back Into A Real Flow

1

Read vtype to obtain the current SEW, LMUL, tail policy, and mask policy.

2

Interpret the returned value according to the field descriptions and do not attempt to write it back.

3

If VS is Off, enable an available vector context before accessing vector CSRs.

FAQ

Can vtype be accessed from any privilege level?

Its CSR number is URO and it can be read from U-mode, but with the V extension mstatus.VS=Off makes access raise an illegal-instruction exception. With V=1, either vsstatus.VS=Off or mstatus.VS=Off also raises that exception.

What is easiest to miss when using vtype?

vtype is read-only. Do not write it with CSR write instructions; configure it with vsetvli, vsetivli, or vsetvl, and write XLEN-2:8 as zero.