RISC-V vstart CSR Register

Address 0x008Privilege User/VectorAccess RW / XLENUser vector state CSRs

vstart is an XLEN-bit read-write CSR that specifies the element index at which a vector instruction begins execution.

Related Search Terms

vstart CSR vstart 0x008 vector start index vector trap restart RVV vstart

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

VSTART63:0RW

Field Map

Understand vstart By Bit Fields

1 key fields

XLEN-1:0

VSTART

Start element index. Only enough writable bits to hold the largest element index of the maximum VLMAX are required; values beyond the largest element index for the current vtype are reserved.

VSTART (bits XLEN-1:0) — Start element index. Only enough writable bits to hold the largest element index of the maximum VLMAX are required; values beyond the largest element index for the current vtype are reserved.

What This Field Controls

- Start element index. Only enough writable bits to hold the largest element index of the maximum VLMAX are required; values beyond the largest element index for the current vtype are reserved.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

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Official Basis & Search Notes

vstart specifies the element index at which the next vector instruction begins processing.

Table 42 lists vstart as the URW vector CSR at address 0x008.

Vector instructions clear vstart when they complete; illegal-instruction exceptions do not modify it.

RISC-V Unprivileged ISA Manual RISC-V Privileged Architecture Manual

What To Check First When Reading This CSR

- Accessing a vector CSR raises an illegal-instruction exception when mstatus.VS is Off.
- When V=1, accessing a vector CSR raises an illegal-instruction exception if either mstatus.VS or vsstatus.VS is Off.

Risk Checks Before Writing

- Application programmers should normally not explicitly write a nonzero vstart; it can be substantially slower on some implementations, and some vector instructions raise an illegal-instruction exception.
- A vstart value beyond the largest element index for the current vtype is reserved.

Put It Back Into A Real Flow

On a resumable trap, hardware writes vstart with the element index at which the trap occurred.

A vector instruction begins at vstart and leaves earlier destination elements undisturbed.

At completion, every vector instruction, including vset{i}vl{i}, resets vstart to zero; an illegal-instruction exception does not modify it.

FAQ

When does hardware write vstart?

vstart is an XLEN-bit read-write CSR that specifies the element index at which a vector instruction begins execution.