vsctrctl (0x24E) is the 64-bit VS-mode CTR control CSR when H is implemented; when V=1 it substitutes for sctrctl.
Selects transfer recording in VU-mode; this field is mandatory writable.
U (bit 0) — Selects transfer recording in VU-mode; this field is mandatory writable.
VU-mode recording is not selected.
VU-mode recording is selected.
Selects transfer recording in VS-mode; this field is mandatory writable.
S (bit 1) — Selects transfer recording in VS-mode; this field is mandatory writable.
VS-mode recording is not selected.
VS-mode recording is selected.
Reserved. Software ignores reads and preserves these bits on writes; undefined implementations are read-only zero.
WPRI (bits 6:2) — Reserved. Software ignores reads and preserves these bits on writes; undefined implementations are read-only zero.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
↗Open Official ManualEnables Return Address Stack (RAS) emulation mode; when set, calls are recorded, returns pop entries, co-routine swaps act as a return plus call, other transfer types are inhibited, and bits 47:32 plus xTE are ignored.
RASEMU (bit 7) — Enables Return Address Stack (RAS) emulation mode; when set, calls are recorded, returns pop entries, co-routine swaps act as a return plus call, other transfer types are inhibited, and bits 47:32 plus xTE are ignored.
Use normal CTR recording behavior.
Enable RAS-emulation recording behavior and ignore the transfer filters and external-trap enable bits.
When VS-mode recording is not selected, permits recording external traps to VS-mode; if external-trap recording is implemented and H is implemented, vsctrctl.STE must be implemented.
STE (bit 8) — When VS-mode recording is not selected, permits recording external traps to VS-mode; if external-trap recording is implemented and H is implemented, vsctrctl.STE must be implemented.
Do not additionally permit recording external traps to VS-mode.
Permit recording external traps to VS-mode.
Reserved. Software ignores reads and preserves these bits on writes; undefined implementations are read-only zero.
WPRI (bits 10:9) — Reserved. Software ignores reads and preserves these bits on writes; undefined implementations are read-only zero.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
↗Open Official ManualSets sctrstatus.FROZEN when a breakpoint exception traps to VS-mode; this field is mandatory writable.
BPFRZ (bit 11) — Sets sctrstatus.FROZEN when a breakpoint exception traps to VS-mode; this field is mandatory writable.
Breakpoint traps do not trigger this automatic freeze.
A qualifying breakpoint trap sets FROZEN.
Sets sctrstatus.FROZEN when a local-counter-overflow interrupt traps to VS-mode; it must be writable when Sscofpmf is implemented.
LCOFIFRZ (bit 12) — Sets sctrstatus.FROZEN when a local-counter-overflow interrupt traps to VS-mode; it must be writable when Sscofpmf is implemented.
LCOFI traps do not trigger this automatic freeze.
A qualifying LCOFI trap sets FROZEN.
Reserved. Software ignores reads and preserves these bits on writes; undefined implementations are read-only zero.
WPRI (bits 32:13) — Reserved. Software ignores reads and preserves these bits on writes; undefined implementations are read-only zero.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
↗Open Official ManualInhibits recording exceptions.
EXCINH (bit 33) — Inhibits recording exceptions.
Do not inhibit exceptions recording through this bit.
Inhibit exceptions recording.
Inhibits recording interrupts.
INTRINH (bit 34) — Inhibits recording interrupts.
Do not inhibit interrupts recording through this bit.
Inhibit interrupts recording.
Inhibits recording trap returns.
TRETINH (bit 35) — Inhibits recording trap returns.
Do not inhibit trap returns recording through this bit.
Inhibit trap returns recording.
Enables recording not-taken branches; this is an enable bit rather than an inhibit bit.
NTBREN (bit 36) — Enables recording not-taken branches; this is an enable bit rather than an inhibit bit.
Do not record not-taken branches.
Record qualifying not-taken branches.
Inhibits recording taken branches.
TKBRINH (bit 37) — Inhibits recording taken branches.
Do not inhibit taken branches recording through this bit.
Inhibit taken branches recording.
Reserved. Software ignores reads and preserves these bits on writes; undefined implementations are read-only zero.
WPRI (bits 39:38) — Reserved. Software ignores reads and preserves these bits on writes; undefined implementations are read-only zero.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
↗Open Official ManualInhibits recording indirect calls.
INDCALLINH (bit 40) — Inhibits recording indirect calls.
Do not inhibit indirect calls recording through this bit.
Inhibit indirect calls recording.
Inhibits recording direct calls.
DIRCALLINH (bit 41) — Inhibits recording direct calls.
Do not inhibit direct calls recording through this bit.
Inhibit direct calls recording.
Inhibits recording indirect jumps without linkage.
INDJMPINH (bit 42) — Inhibits recording indirect jumps without linkage.
Do not inhibit indirect jumps without linkage recording through this bit.
Inhibit indirect jumps without linkage recording.
Inhibits recording direct jumps without linkage.
DIRJMPINH (bit 43) — Inhibits recording direct jumps without linkage.
Do not inhibit direct jumps without linkage recording through this bit.
Inhibit direct jumps without linkage recording.
Inhibits recording co-routine swaps.
CORSWAPINH (bit 44) — Inhibits recording co-routine swaps.
Do not inhibit co-routine swaps recording through this bit.
Inhibit co-routine swaps recording.
Inhibits recording function returns.
RETINH (bit 45) — Inhibits recording function returns.
Do not inhibit function returns recording through this bit.
Inhibit function returns recording.
Inhibits recording other indirect jumps with linkage.
INDLJMPINH (bit 46) — Inhibits recording other indirect jumps with linkage.
Do not inhibit other indirect jumps with linkage recording through this bit.
Inhibit other indirect jumps with linkage recording.
Inhibits recording other direct jumps with linkage.
DIRLJMPINH (bit 47) — Inhibits recording other direct jumps with linkage.
Do not inhibit other direct jumps with linkage recording through this bit.
Inhibit other direct jumps with linkage recording.
Reserved. Software ignores reads and preserves these bits on writes; undefined implementations are read-only zero.
WPRI (bits 59:48) — Reserved. Software ignores reads and preserves these bits on writes; undefined implementations are read-only zero.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
↗Open Official ManualWARL custom bits; value 0 must correspond to standard CTR behavior.
Custom (bits 63:60) — WARL custom bits; value 0 must correspond to standard CTR behavior.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
↗Open Official Manualvsctrctl is the guest-visible CTR control copy. When V=1 it substitutes for sctrctl so a guest can configure VS/VU recording and filtering; when V=0 those guest settings do not affect host CTR behavior.
Confirm that H, Smctr/Ssctr, and Sscsrind are implemented, and check state-enable gates.
In a V=1 guest, configure VS/VU recording enables, STE, freeze, and filter fields through the sctrctl alias.
Read CTR entries through vsiselect/vsireg* or the siselect/sireg* aliases; sctrstatus.FROZEN and depth remain shared supervisor CTR state.
When H is implemented, vsctrctl is the VS-mode version of sctrctl; when V=1, accesses to sctrctl are substituted with vsctrctl.
No. The spec states that RV32 cannot access xctrctl[63:32], and no vsctrctlh high-half CSR is defined.