Does AMOMIN.D place the new memory result in rd?
No. On success rd receives old 64-bit memory and the signed minimum result is stored in memory; rd=x0 discards register writeback.
AMOMIN.D
RISC-V AMOMIN.D Instruction Details
Instruction ManualR-typeRV64 atomic signed minimum: rd receives the old 64-bit memory value; memory receives signed min(old, rs2Low64).
Instruction Syntax
amomin.d rd, rs2, (rs1)
Operand Breakdown
rd: receives the old memory value read atomically; for AMOCAS, its pre-execution value also supplies the compare value.
rs1: directly supplies the atomic-memory address; AMO assembly syntax has no offset immediate field.
rs2: supplies the AMO source data; for AMOCAS, it is the swap value stored when the comparison matches.
AMO-type is this site's presentation label for the AMO-specific R-type field layout: funct5, aq, rl, rs2, rs1, funct3, rd, and the AMO opcode encode the operation.
AZaamoAtomic Operation
Instruction Behavior
AMOMIN.D (A / Zaamo, RV64) atomically reads, modifies and writes the 64-bit doubleword at rs1: compare old memory with the low 64 bits of the pre-execution rs2 as signed integers, store the selected bit pattern at the original address, and return old memory in rd. rd=x0 discards only register writeback; the memory operation still occurs. Overlapping registers use pre-execution source values. aq/rl add ordering only in the accessed memory or I/O domain; use FENCE for cross-domain ordering.
AMOMIN.D Atomic Decode And Execute Animation
Shows A / Zaamo doubleword atomic field decode, aq/rl ordering bits, a memory read, and RMW state update.
rd
rs2
rs1
amomin.d,,()
Execution Context
31..27
26
25
24..20
19..15
14..12
11..7
6..0
10000
funct5
0
aq
0
rl
01011
rs2
01010
rs1
011
funct3
00101
rd
0101111
opcode
Atomic Data Path
instruction
0x80B532AF
opcode
0101111 -> AMO
funct3
011 -> doubleword width
funct5
10000 -> AMOMIN.D
aq / rl
0/0 -> unordered
rd / rs2 / rs1
t0(x5) / a1(x11)=0x0000000000000001 / a0(x10)=0x0000000000001000
memory read
mem[0x0000000000001000] -> old doubleword 0x8000000000000000
RMW
(-9223372036854775808 <= 1) = true -> 0x8000000000000000
rd / memory
t0(x5) = 0x8000000000000000; mem[0x0000000000001000] = 0x8000000000000000
Current Step
Concept Step: receive the 32-bit atomic instruction encoding
A / Zaamo-extension doubleword atomic instructions use a 32-bit encoding; the animation starts by splitting the fields.
encoding: 0x80B532AF
syntax : amomin.d t0(x5), a1(x11), (a0(x10))
result : t0(x5) = 0x8000000000000000; mem[0x0000000000001000] = 0x8000000000000000
Signed 64-bit Doubleword Comparison
old doubleword
0x8000000000000000 (-9223372036854775808)
rs2 doubleword
0x0000000000000001 (1)
comparison
(old <= rs2) = true -> old value
memory result
0x8000000000000000
AMOMIN.D selects the memory writeback doubleword using a signed 64-bit comparison; this is not a per-bit logical operation.
Assumes the region supports this AMO and the access succeeds. Shows comparison, old-value return, memory update and aq/rl ordering in the accessed domain. Steps are a teaching sequence; access faults, CPU cache coherence, pipelines and timing are not modeled.
Quick Understanding & Search Notes
AMOMIN.D stores the signed minimum to memory and, on success, returns old memory in rd; rd=x0 discards only register writeback.
funct5=10000, funct3=011, and opcode=0101111 identify AMOMIN.D; aq/rl bits do not change the data calculation.
On success rd receives old 64-bit memory and the selected signed minimum is stored at the original address; rd=x0 discards only register writeback.
Normally requires 8-byte natural alignment. Misalignment raises address-misaligned or access-fault unless the region has a misaligned atomicity granule PMA and all accessed bytes lie in one granule. The region must support this width and arithmetic AMO.
AMOMIN.D uses a signed 64-bit comparison to select the writeback value; do not explain min/max with a per-bit logical view.
Common Usage Scenarios
Atomic & Sync
Successful 64-bit access example: a2=0x1000, old memory=5, a1=3; amomin.d a0, a1, (a2) returns a0=5 and updates memory to 3. The address is naturally aligned and the region supports this AMO.
Signed Comparisons
Successful 64-bit access example: a2=0x1000, old memory=5, a1=3; amomin.d a0, a1, (a2) returns a0=5 and updates memory to 3. The address is naturally aligned and the region supports this AMO.
RV64 Operations
Successful 64-bit access example: a2=0x1000, old memory=5, a1=3; amomin.d a0, a1, (a2) returns a0=5 and updates memory to 3. The address is naturally aligned and the region supports this AMO.
Pre-Use Checklist
Syntax Check
- rd, rs2, and rs1 select x0–x31 or their ABI names; syntax is rd, rs2, (rs1), with no rs3 or offset immediate.
- Check funct5 for the operation and funct3 for access width; aq/rl are separate ordering bits, not a fixed funct7 constant.
Semantic Check
- Check natural alignment or the misaligned atomicity granule PMA condition; the target region must support this AMO width and operation.
- On success, rd receives old memory and the computed result goes to memory; rd=x0 discards only register writeback. On RV64, AMO.W sign-extends the old word and uses only rs2[31:0].
Pitfalls / Common Confusions
On success rd receives old memory, not the new signed minimum result; rd=x0 discards writeback.
Normally requires 8-byte natural alignment. Misalignment raises address-misaligned or access-fault unless the region has a misaligned atomicity granule PMA and all accessed bytes lie in one granule. The region must support this width and arithmetic AMO.
Compare 64-bit signed integers using the pre-execution rs2 value.
AMO.D is RV64-only, with 64-bit memory and register data.
aq/rl do not change the data result or imply ordering in the other memory/I/O domain.
FAQ
Do aq/rl bits change the signed minimum result of AMOMIN.D?
No. aq/rl only affect memory-ordering constraints; they do not change this AMO.D instruction's 64-bit data result.