AMOMIN.D
RISC-V AMOMIN.D Instruction Details
Instruction ManualR-typeAtomically compute signed minimum of 64-bit doubleword: rd = *rs1, *rs1 = min(*rs1, rs2) (RV64 only)
Instruction Syntax
amomin.d rd, rs2, (rs1)
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
AZaamoAtomic Operation
Instruction Behavior
AMOMIN.D atomically loads the 64-bit signed value from the address in rs1 into rd, compares with rs2, stores the signed minimum back. This is an RV64A instruction. Supports aq/rl bits.
Common Usage Scenarios
Comparison & Detection
Understand this scenario with real code like «amomin.d a0, a1, (a2) # a0 = *a2; *a2 = min(*a2, a1) (64-bit signed)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Returns old value before operation