Does AMOMINU.H zero-extend rd?
No. Zabha AMO.H sign-extends the old value into rd; the U in AMOMINU.H/AMOMAXU.H only means unsigned comparison.
AMOMINU.H
RISC-V AMOMINU.H Instruction Details
Instruction ManualAMO-typeAMOMINU.H atomically reads the old halfword, sign-extends it into rd, and compares the old halfword and rs2[15:0] as unsigned 16-bit values and writes the smaller value.
Instruction Syntax
amominu.h rd, rs2, (rs1)
Syntax is rd, rs2, (rs1). The three fields select x0–x31 or ABI names, with no offset immediate or rs3.
funct5=11000, funct3=001, opcode=0101111; aq at bit26 and rl at bit25 are independent ordering bits.
RV32/RV64 Zabha (requires Zaamo): rd receives the sign-extended old 16-bit memory value; only the low 16 rs2 bits compute new memory.
The region must support this AMO width and operation. Use two-byte alignment, or a PMA with all accessed bytes in one misaligned atomicity granule; otherwise misalignment raises address-misaligned or access-fault.
Sources use pre-execution values; rd=x0 discards register writeback while memory read-modify-write still occurs. aq/rl orders only the accessed memory/I/O domain.
ZabhaAtomic
Instruction Behavior
AMOMINU.H is a halfword AMO from Zabha, which depends on Zaamo. It performs a 16-bit read-modify-write, writes the sign-extended old memory halfword to rd, and compares the old halfword and rs2[15:0] as unsigned 16-bit values, storing the smaller value. The aq/rl bits provide release-consistency ordering without changing the data computation.
AMOMINU.H Atomic Decode And Execute Animation
Shows Zabha (requires Zaamo) halfword atomic field decode, aq/rl ordering bits, a memory read, and RMW state update.
rd
rs2
rs1
amominu.h,,()
Execution Context
31..27
26
25
24..20
19..15
14..12
11..7
6..0
11000
funct5
0
aq
0
rl
01011
rs2
01010
rs1
001
funct3
00101
rd
0101111
opcode
Atomic Data Path
instruction
0xC0B512AF
opcode
0101111 -> AMO
funct3
001 -> halfword width
funct5
11000 -> AMOMINU.H
aq / rl
0/0 -> unordered
rd / rs2 / rs1
t0(x5) / a1(x11)[15:0]=0x0001 / a0(x10)=0x00001000
memory read
mem[0x00001000] -> old halfword 0x8000
RMW
Not computed
rd / memory
t0(x5) = unspecified initial value; mem[0x00001000] = 0x8000
Current Step
Concept Step: receive the 32-bit atomic instruction encoding
Zabha depends on Zaamo; Zabha-extension halfword atomic instructions use a 32-bit encoding; the animation starts by splitting the fields.
encoding: 0xC0B512AF
syntax : amominu.h t0(x5), a1(x11), (a0(x10))
Pending result : Not computed
Current architectural state
t0(x5) = unspecified initial value; mem[0x00001000] = 0x8000
Assumes Zabha and Zaamo at the selected XLEN, successful fetch, a region supporting this width and operation, and a successful access. A misaligned halfword requires the stated PMA condition. Sources use pre-execution values; aq/rl orders only the accessed domain. Steps are a teaching sequence.
Quick Understanding & Search Notes
AMOMINU.H is a Zabha halfword AMO: it atomically reads the old 16-bit memory value, sign-extends that old value into rd, and compares the old halfword and rs2[15:0] as unsigned 16-bit values and writes the smaller value.
The encoding uses AMO major opcode 0101111, funct3=001 for halfword width, and funct5 to select the specific AMO operation.
All AMO.H forms write the sign-extended old halfword to rd; the unsigned suffix only changes min/max comparison interpretation.
rs2 contributes only its low 16 bits; the address normally has 2-byte alignment, while a PMA condition can relax the alignment exception; aq/rl only affect memory ordering.
Common Usage Scenarios
Atomic & Sync
RV32/RV64 Zabha+Zaamo, a1=0x1000, old 16-bit memory=0x8000 and a2=1; assume a supporting region and normal completion: amominu.h a0, a2, (a1) returns a0=0xFFFF8000 (RV32) or 0xFFFFFFFFFFFF8000 (RV64) and writes 0x0001 to memory. The data operation is 16-bit unsigned minimum.
Pre-Use Checklist
Syntax Check
- Syntax is rd, rs2, (rs1). The three fields select x0–x31 or ABI names, with no offset immediate or rs3.
- funct5=11000, funct3=001, opcode=0101111; aq at bit26 and rl at bit25 are independent ordering bits.
Semantic Check
- RV32/RV64 Zabha (requires Zaamo): rd receives the sign-extended old 16-bit memory value; only the low 16 rs2 bits compute new memory.
- The region must support this AMO width and operation. Use two-byte alignment, or a PMA with all accessed bytes in one misaligned atomicity granule; otherwise misalignment raises address-misaligned or access-fault.
- Sources use pre-execution values; rd=x0 discards register writeback while memory read-modify-write still occurs. aq/rl orders only the accessed memory/I/O domain.
Pitfalls / Common Confusions
rd receives the old memory halfword sign-extended to XLEN, not the newly written memory value.
Only the low 16 bits of rs2 participate in the halfword computation; upper rs2 bits do not affect this AMO.H data result.
Unsigned only changes the min/max comparison; the old value written to rd is still sign-extended, not zero-extended.
A halfword address normally needs natural alignment; a PMA can relax the alignment-exception condition when all accessed bytes are in one misaligned atomicity granule.
FAQ
How much memory does AMOMINU.H modify?
Architecturally it modifies only the target 16-bit halfword and computes the new memory value at halfword width; neighboring bytes are not part of that data result.