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C.AND

RISC-V C.AND Instruction Details

Instruction ManualC-type

RV32/RV64: AND the XLEN-bit values of rd' and rs2' (x8–x15), then write rd'.

Instruction Syntax

c.and rd', rs2'
Operand Breakdown
RV32/RV64, C 2.0 or Zca; 16-bit CA format.
Three-bit rd'/rs1' and rs2' both select x8–x15; there is no immediate.
AND the two old XLEN-bit sources and write rd'; equal register names use the same old value.
CCompressed Instruction
Related Search Terms
C.AND instructionRISC-V C.ANDc.and CA encodingc.and C Zcac.and XLEN bitwise ANDc.and x8 x15c.and overlapping registers

Instruction Behavior

C.AND (CA format, x8-x15 only) computes bitwise AND of rd' and rs2', writes to rd'. Expands to and rd',rd',rs2'.

C.AND Compressed Encoding Lab

Explore the 16-bit encoding, operands, calculation, and architectural result.

c.and,

RV32C/RV64C / Zca

0x000000000000F0F0 & 0x0000000000000FF0 x8 <- 0x00000000000000F0

16-bit encoding fields

15..10: funct6
100011
9..7: rd'/rs1'
000
6..5: funct2
11
4..2: rs2'
001
1..0: op
01
rd'/rs1' = 000 -> x8
rs2' = 001 -> x9
x8 = 0x000000000000F0F0
x9 = 0x0000000000000FF0
0x000000000000F0F0 AND 0x0000000000000FF0 = 0x00000000000000F0
Architectural state has not been committed.

Quick Understanding & Search Notes

RV32/RV64: AND the XLEN-bit values of rd' and rs2' (x8–x15), then write rd'.

CA: funct6=100011, funct2=11, op=01; rd'/rs1' and rs2' are three-bit fields.
Both operands are registers x8–x15; there is no immediate operand.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, Version 20260120

Common Usage Scenarios

Bit Operations & Masks

RV32/RV64, x8=0xf0f0 and x9=0x0ff0: c.and x8, x9 gives x8=0x00f0; both registers are in x8–x15.

Pre-Use Checklist

Syntax Check
  • RV32/RV64, C 2.0 or Zca; 16-bit CA format.
  • Three-bit rd'/rs1' and rs2' both select x8–x15; there is no immediate.
Semantic Check
  • AND the two old XLEN-bit sources and write rd'; equal register names use the same old value.

Pitfalls / Common Confusions

Only x8-x15 registers (CA format, 3-bit register fields)
There is no immediate operand; both operands are compressed x8-x15 registers

FAQ

Can both operands name the same register?

Yes. x & x = x; both operands use the same old register value and the result writes rd'.

Can it AND x1 or an immediate?

No. Both three-bit compressed fields encode only x8–x15. C.AND has no immediate; the compressed immediate form is C.ANDI.