Is it always equivalent to a same-named 32-bit instruction?
Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.
C.AND
RISC-V C.AND Instruction Details
Instruction ManualC-typeBitwise AND of rd' and rs2', write to rd'. CA format.
Instruction Syntax
c.and rd, rs2
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CCompressed Instruction
Instruction Behavior
C.AND (CA format, x8-x15 only) computes bitwise AND of rd' and rs2', writes to rd'. Expands to and rd',rd',rs2'.
Quick Understanding & Search Notes
C.AND is the 16-bit encoding form for compressed bitwise AND; its semantics and encodable register/immediate ranges must be read from the official C extension rules.
Compressed instructions often restrict register sets, immediate encodings, or destination registers; illegal combinations can be reserved.
Examples show assembly intent; actual encoding constraints follow the official C/Zc tables.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «c.and x8, x9 # x8 &= x9».
Multiplication & Division
Understand this scenario with real code like «c.and x8, x9 # x8 &= x9».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is C-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Only x8-x15 registers (CA format, 3-bit register fields)
Compared to 32-bit equivalent, no immediate variant
FAQ
Why do register restrictions matter?
Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.