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C.AND

RISC-V C.AND Instruction Details

Instruction ManualC-type

Bitwise AND of rd' and rs2', write to rd'. CA format.

Instruction Syntax

c.and rd', rs2'
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CCompressed Instruction
Related Search Terms
C.AND instructionRISC-V C.ANDc.and syntaxc.and encodingc.and Cc.and compressed instructioncompressed bitwise AND

Instruction Behavior

C.AND (CA format, x8-x15 only) computes bitwise AND of rd' and rs2', writes to rd'. Expands to and rd',rd',rs2'.

C.AND Decode & Execute Animation

Shows only official 16-bit decode, operands, computation, and architectural state; it does not simulate a pipeline, cache, or timing.

c.and,
Execution context
16-bit encoding fields
15..10
funct6
100011
9..7
rd'/rs1'
000
6..5
funct2
11
4..2
rs2'
001
1..0
op
01
Execution data path
x8 = 0x000000000000F0F0
x9 = 0x0000000000000FF0
0x000000000000F0F0 AND 0x0000000000000FF0 = 0x00000000000000F0
Architectural state has not been committed.

Quick Understanding & Search Notes

C.AND is the 16-bit encoding form for compressed bitwise AND; its semantics and encodable register/immediate ranges must be read from the official C extension rules.

Compressed instructions often restrict register sets, immediate encodings, or destination registers; illegal combinations can be reserved.
Examples show assembly intent; actual encoding constraints follow the official C/Zc tables.
RISC-V Unprivileged ISA Manual, C Extension

Common Usage Scenarios

Bit Operations & Masks

Understand this scenario with real code like «c.and x8, x9 # x8 &= x9».

Pre-Use Checklist

Syntax Check
  • Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
  • Confirm rd/rs1'/rs2' fields map to x8–x15.
Semantic Check
  • Note the limited operand space of compressed instructions.
  • Verify this compressed instruction has a corresponding 32-bit expansion.

Pitfalls / Common Confusions

Only x8-x15 registers (CA format, 3-bit register fields)
There is no immediate operand; both operands are compressed x8-x15 registers

FAQ

Is it always equivalent to a same-named 32-bit instruction?

Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.

Why do register restrictions matter?

Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.