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C.OR

RISC-V C.OR Instruction Details

Instruction ManualC-type

Bitwise OR of rd' and rs2', write to rd'. CA format.

Instruction Syntax

c.or rd', rs2'
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CCompressed Instruction
Related Search Terms
C.OR instructionRISC-V C.ORc.or syntaxc.or encodingc.or Cc.or compressed instructioncompressed bitwise OR

Instruction Behavior

C.OR (CA format, x8-x15 only) computes bitwise OR of rd' and rs2', writes to rd'. Expands to or rd',rd',rs2'.

C.OR Decode & Execute Animation

Shows only ISA-visible 16-bit encoding, operands, and state, not a pipeline, cache, or timing.

c.or,
Execution context
x10 <- 0x00F0000F | 0x0000FF00 = 0x00F0FF0F
16-bit encoding fields
15..10
funct6
100011
9..7
rd'/rs1'
010
6..5
funct2
10
4..2
rs2'
011
1..0
op
01
Execution data path
Input to result
x10 <- 0x00F0000F | 0x0000FF00 = 0x00F0FF0F
Concrete calculation
The Calculate stage shows the equation for the current inputs.
Architectural state
Architectural state is written only at Commit result.
Architectural result

Continue to Commit result to reveal architectural state.

Quick Understanding & Search Notes

C.OR uses the CA format: rd'/rs1' and rs2' each map to x8-x15, and the result is written to rd'.

The CA format has no immediate; its two 3-bit compressed-register fields select rd'/rs1' and rs2'.
C.OR performs XLEN-wide bitwise OR and writes the result back to rd'.
RISC-V Unprivileged ISA Manual, C Extension

Common Usage Scenarios

Bit Operations & Masks

Understand this scenario with real code like «c.or x8, x9 # x8 = x8 | x9».

Pre-Use Checklist

Syntax Check
  • Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
  • Confirm rd/rs1'/rs2' fields map to x8–x15.
Semantic Check
  • Note the limited operand space of compressed instructions.
  • Verify this compressed instruction has a corresponding 32-bit expansion.

Pitfalls / Common Confusions

Only x8-x15 registers (CA format, 3-bit register fields)
There is no immediate operand; rd' is both source and destination

FAQ

Is it always equivalent to a same-named 32-bit instruction?

Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.

Why do register restrictions matter?

Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.