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CM.JALT

RISC-V CM.JALT Instruction Details

Instruction ManualC-type

Indirect jump via table, save return address

Instruction Syntax

cm.jalt index
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
ZcmtJump & Control TransferCompressed Instruction
Related Search Terms
CM.JALT instructionRISC-V CM.JALTcm.jalt syntaxcm.jalt encodingcm.jalt Zcmtcm.jalt compressed instructioncompressed table jump and link

Instruction Behavior

CM.JALT (Zcmt) looks up target from JVT CSR table by index, writes pc+2 to x1(ra), then jumps. Reuses c.fsdsp encoding, incompatible with Zcd (C+D). Part of Zcmt, depends on Zca and Zicsr.

Quick Understanding & Search Notes

CM.JALT is the 16-bit encoding form for compressed table jump and link; its semantics and encodable register/immediate ranges must be read from the official Zc extension rules.

Compressed instructions often restrict register sets, immediate encodings, or destination registers; illegal combinations can be reserved.
Examples show assembly intent; actual encoding constraints follow the official C/Zc tables.
RISC-V Unprivileged ISA Manual, Zc Extensions

Common Usage Scenarios

Branch & Jump

Understand this scenario with real code like «cm.jalt 5 # jump-and-link via table entry 5».

Compressed & Code Size

Understand this scenario with real code like «cm.jalt 5 # jump-and-link via table entry 5».

Function Call & Return

Understand this scenario with real code like «cm.jalt 5 # jump-and-link via table entry 5».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is C-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Incompatible with Zcd (reuses c.fsdsp encoding)
Requires JVT CSR configuration
Link address is pc+2 (not pc+4)

FAQ

Is it always equivalent to a same-named 32-bit instruction?

Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.

Why do register restrictions matter?

Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.