Is the table entry an ordinary data load?
No. Instruction and table entry are two implicit fetches requiring execute permission; read permission is irrelevant. The entry follows current data endianness.
CM.JT
RISC-V CM.JT Instruction Details
Instruction ManualC-typeIndirect jump via table
Instruction Syntax
cm.jt index
Operand Breakdown
RV32/RV64 Zcmt depends on Zca+Zicsr and conflicts with Zcd; 16-bit CMJT format with index in bits[9:2].
CM.JT uses index=0-31 and does not write ra; the index range distinguishes the two instructions sharing this encoding.
With jvt.mode=0, the table address is jvt.base + index×(XLEN/8), truncated to XLEN bits; clear bit 0 of the fetched target.
jvt.base is at least 64-byte aligned. Entries follow data endianness; both implicit fetches require execute permission. Applicable stateen controls must permit access.
Reserved modes do not define an ordinary jump. On either fetch fault, xEPC identifies this instruction and xTVAL, if nonzero, identifies the faulting fetch address. No direct single 32-bit equivalent encoding exists.
ZcmtJump & Control TransferCompressed Instruction
Instruction Behavior
CM.JT (Zcmt) decodes only for index 0-31. It fetches an instruction-memory table entry at the JVT CSR base plus index<<2 on RV32 or index<<3 on RV64, then writes the entry with bit 0 cleared to pc. Only jvt.mode=0 defines this behavior; a reserved mode makes the instruction reserved. It reuses c.fsdsp encodings, is incompatible with Zcd, and Zcmt depends on Zca and Zicsr.
CM.JT Decode & Execute Animation
Shows only official compressed fields, conditions, and architectural state; it does not model a pipeline, cache, or timing.
cm.jt
Execution context
Assumes Zca, Zicsr and Zcmt are available and jvt access is permitted, including applicable stateen controls. Zcmt table entries follow current data endianness and are fetched as instruction memory; JVT base must be at least 64-byte aligned.
cm.jt 3 → PC <- 0x80001000
16-bit encoding fields
15..13
funct3
101
12..10
fixed
000
9..2
index
00000011
1..0
op
10
Execution data path
CM.JT has 8-bit index=3 in bits[9:2]; it is below 32, so decodes as this instruction.
0x0000200C = 0x00002000 + (3 << 2); PC' = JVT[0x0000200C] & ~1 = 0x80001001 & ~1 = 0x80001000
PC <- 0x80001000
Architectural state has not been committed.
Quick Understanding & Search Notes
CM.JT uses index 0-31 to select a JVT entry and jumps to the fetched target with bit 0 cleared without writing ra.
index>=32 decodes as CM.JALT; CM.JT requires index 0-31.
Only jvt.mode=0 defines table jump; a fault on either implicit fetch does not commit the ordinary jump.
jvt.base is at least 64-byte aligned; entries follow current data endianness. On a fetch exception, xEPC identifies this instruction and xTVAL, if nonzero, is the faulting fetch address.
Common Usage Scenarios
Branch & Jump
RV32 Zcmt, jvt.mode=0, base=0x2000, entry[0x200c]=0x80001001: cm.jt 3 writes PC=0x80001000 without writing ra, when fetches complete and access is permitted.
Compressed & Code Size
RV32 Zcmt, jvt.mode=0, base=0x2000, entry[0x200c]=0x80001001: cm.jt 3 writes PC=0x80001000 without writing ra, when fetches complete and access is permitted.
Pre-Use Checklist
Syntax Check
- RV32/RV64 Zcmt depends on Zca+Zicsr and conflicts with Zcd; 16-bit CMJT format with index in bits[9:2].
- CM.JT uses index=0-31 and does not write ra; the index range distinguishes the two instructions sharing this encoding.
Semantic Check
- With jvt.mode=0, the table address is jvt.base + index×(XLEN/8), truncated to XLEN bits; clear bit 0 of the fetched target.
- jvt.base is at least 64-byte aligned. Entries follow data endianness; both implicit fetches require execute permission. Applicable stateen controls must permit access.
- Reserved modes do not define an ordinary jump. On either fetch fault, xEPC identifies this instruction and xTVAL, if nonzero, identifies the faulting fetch address. No direct single 32-bit equivalent encoding exists.
Pitfalls / Common Confusions
index must be 0-31; 32-255 decodes as CM.JALT.
jvt.mode must be 0; a reserved mode makes the instruction reserved.
The entry is fetched as instruction memory, bit 0 of the target is cleared, and this instruction does not write ra.
Both implicit fetches require execute permission; applicable stateen controls must permit jvt access.
FAQ
How does index select linking?
In the shared encoding, index=0-31 decodes as CM.JT without writing ra; 32-255 decodes as CM.JALT, writing ra=PC+2 on completion. This behavior is defined for jvt.mode=0.