Is it always equivalent to a same-named 32-bit instruction?
Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.
CM.MVSA01
RISC-V CM.MVSA01 Instruction Details
Instruction ManualC-typeMove a0 and a1 into two different s0-s7 registers
Instruction Syntax
cm.mvsa01 r1s', r2s'
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
ZcmpStack & FunctionsCompressed Instruction
Instruction Behavior
CM.MVSA01 (Zcmp) writes a0 into r1s' and a1 into r2s'; the destinations are UABI s0-s7 and must differ. The two writes are atomically visible. On RV32E, encodings selecting s2-s7 for either specifier are reserved. It reuses c.fsdsp encodings, is incompatible with Zcd, and Zcmp depends on Zca.
CM.MVSA01 Decode & Execute Animation
Shows only official compressed fields, conditions, and architectural state; it does not model a pipeline, cache, or timing.
cm.mvsa01,
Execution context
Zcmp depends on Zca and is incompatible with Zcd; RV32E reserves s2-s7 specifiers.
s0 <- 0x11223344; s1 <- 0x55667788 (atomic)
16-bit encoding fields
15..13
funct3
101
12..10
fixed
011
9..7
r1s'
000
6..5
fixed
01
4..2
r2s'
001
1..0
op
10
Execution data path
The s-register specifiers restore s0 and s1 (encoded values 0 and 0).
s0 <- a0 (0x11223344); s1 <- a1 (0x55667788)
s0 <- 0x11223344; s1 <- 0x55667788 (atomic)
Architectural state has not been committed.
Quick Understanding & Search Notes
CM.MVSA01 is a Zcmp 16-bit register-move instruction: a0/a1 atomically write two distinct UABI s0-s7 destinations.
The official operation is X[xreg1]=X[10], X[xreg2]=X[11]; do not reverse it into saved registers -> a0/a1.
r1s' and r2s' must differ and encode UABI s0-s7; RV32E selections of s2-s7 are reserved.
Common Usage Scenarios
Data Storing
Understand this scenario with real code like «cm.mvsa01 s0, s1 # s0 = a0; s1 = a1».
Function Call & Return
Understand this scenario with real code like «cm.mvsa01 s0, s1 # s0 = a0; s1 = a1».
Pre-Use Checklist
Syntax Check
- Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
- Confirm rd/rs1'/rs2' fields map to x8–x15.
Semantic Check
- Note the limited operand space of compressed instructions.
- Verify this compressed instruction has a corresponding 32-bit expansion.
Pitfalls / Common Confusions
r1s' and r2s' are destination registers; the direction is a0/a1 -> s0-s7.
The two destination registers must differ and be UABI s0-s7.
RV32E encodings selecting s2-s7 are reserved, and both s-register writes are atomically visible.
Incompatible with Zcd.
FAQ
Why do register restrictions matter?
Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.