Is it always equivalent to a same-named 32-bit instruction?
Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.
CM.MVSA01
RISC-V CM.MVSA01 Instruction Details
Instruction ManualC-typeMove a0 and a1 into two different s0-s7 registers
Instruction Syntax
cm.mvsa01 r1s', r2s'
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
ZcmpStack & FunctionsCompressed Instruction
Instruction Behavior
CM.MVSA01 (Zcmp) writes a0 into r1s' and a1 into r2s'; both destination registers are from s0-s7 and must be different. It is used to save a0/a1 values into s0-s7. The instruction reuses c.fsdsp encodings, is incompatible with Zcd, belongs to Zcmp, and depends on Zca.
Quick Understanding & Search Notes
CM.MVSA01 is a Zcmp 16-bit register-move instruction whose direction is from a0/a1 into two different s0-s7 destination registers.
The official operation is X[xreg1]=X[10], X[xreg2]=X[11]; do not reverse it into saved registers -> a0/a1.
r1s' and r2s' must be different, and the encoding covers only s0-s7.
Common Usage Scenarios
Data Storing
Understand this scenario with real code like «cm.mvsa01 s0, s1 # s0 = a0; s1 = a1».
Function Call & Return
Understand this scenario with real code like «cm.mvsa01 s0, s1 # s0 = a0; s1 = a1».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is C-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
r1s' and r2s' are destination registers; the direction is a0/a1 -> s0-s7.
The two destination registers must be different and must come from s0-s7.
Incompatible with Zcd.
FAQ
Why do register restrictions matter?
Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.