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CM.POPRETZ

RISC-V CM.POPRETZ Instruction Details

Instruction ManualC-type

Restore registers, a0=0, deallocate frame, and ret

Instruction Syntax

cm.popretz {reg_list}, stack_adj
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
ZcmpStack & FunctionsCompressed Instruction
Related Search Terms
CM.POPRETZ instructionRISC-V CM.POPRETZcm.popretz syntaxcm.popretz encodingcm.popretz Zcmpcm.popretz compressed instructioncompressed pop, zero a0, and return

Instruction Behavior

CM.POPRETZ (Zcmp) pops registers in {reg_list}, sets a0 to zero, adjusts sp, then ret. Used for function epilogues returning zero. Differs from POPRET by explicitly zeroing a0. Reuses c.fsdsp encoding. Part of Zcmp, depends on Zca.

Quick Understanding & Search Notes

CM.POPRETZ is the 16-bit encoding form for compressed pop, zero a0, and return; its semantics and encodable register/immediate ranges must be read from the official Zc extension rules.

Compressed instructions often restrict register sets, immediate encodings, or destination registers; illegal combinations can be reserved.
Examples show assembly intent; actual encoding constraints follow the official C/Zc tables.
RISC-V Unprivileged ISA Manual, Zc Extensions

Common Usage Scenarios

Function Call & Return

Understand this scenario with real code like «cm.popretz {ra, s0-s5}, 64 # pop, a0=0, sp+=64, ret».

Immediates & Constants

Understand this scenario with real code like «cm.popretz {ra, s0-s5}, 64 # pop, a0=0, sp+=64, ret».

Register Operations

Understand this scenario with real code like «cm.popretz {ra, s0-s5}, 64 # pop, a0=0, sp+=64, ret».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is C-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Overwrites a0 with zero (destroys any computed return value)
Incompatible with Zcd

FAQ

Is it always equivalent to a same-named 32-bit instruction?

Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.

Why do register restrictions matter?

Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.