RVOPcode
Home/Instructions/CM-POPRETZ
CM.POPRETZ

RISC-V CM.POPRETZ Instruction Details

Instruction ManualC2 (Zcmp CMPP)

Restore registers, a0=0, deallocate frame, and ret

Instruction Syntax

cm.popretz {reg_list}, stack_adj
Operand Breakdown
This is a C2 (Zcmp CMPP)-format instruction. Confirm operand positions based on the assembly syntax.
ZcmpStack & FunctionsCompressed Instruction
Related Search Terms
CM.POPRETZ instructionRISC-V CM.POPRETZcm.popretz syntaxcm.popretz encodingcm.popretz Zcmpcm.popretz compressed instructioncompressed pop, zero a0, and return

Instruction Behavior

CM.POPRETZ (Zcmp) pops registers in {reg_list}, sets a0 to zero, adjusts sp, then ret. Used for function epilogues returning zero. Differs from POPRET by explicitly zeroing a0. Reuses c.fsdsp encoding. Part of Zcmp, depends on Zca.

CM.POPRETZ Decode & Execute Animation

Shows only Zcmp architectural sequences and conditions; access order, grouping, or replay does not imply implementation detail.

cm.popretz {reg_list}, stack_adj
Execution context

Zcmp depends on Zca and is incompatible with Zcd. Correct execution requires idempotent memory at sp; RV32E permits rlist=4-6 only.

a0 <- 0; sp <- 0x00001040; PC <- ra & ~1 = 0x00002000
16-bit encoding fields
15..13
funct3
101
12..8
fixed
11100
7..4
rlist
0111
3..2
spimm
11
1..0
op
10
rlist=7 restores {ra, s0, s1, s2}; spimm=3 adds 48 bytes beyond stack_adj_base.
Pseudocode address mapping: s2 @ 0x0000103C; s1 @ 0x00001038; s0 @ 0x00001034; ra @ 0x00001030. The actual loads can occur in any order, be grouped, or repeat; sp' = 0x00001000 + 64 = 0x00001040.
a0 <- 0; sp <- 0x00001040; PC <- ra & ~1 = 0x00002000
Architectural state has not been committed.

Quick Understanding & Search Notes

CM.POPRETZ is the 16-bit encoding form for compressed pop, zero a0, and return; its semantics and encodable register/immediate ranges must be read from the official Zc extension rules.

Compressed instructions often restrict register sets, immediate encodings, or destination registers; illegal combinations can be reserved.
Examples show assembly intent; actual encoding constraints follow the official C/Zc tables.
RISC-V Unprivileged ISA Manual, Zc Extensions

Common Usage Scenarios

Function Call & Return

Understand this scenario with real code like «cm.popretz {ra, s0-s5}, 64 # pop, a0=0, sp+=64, ret».

Immediates & Constants

Understand this scenario with real code like «cm.popretz {ra, s0-s5}, 64 # pop, a0=0, sp+=64, ret».

Register Operations

Understand this scenario with real code like «cm.popretz {ra, s0-s5}, 64 # pop, a0=0, sp+=64, ret».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is C2 (Zcmp CMPP).
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Overwrites a0 with zero (destroys any computed return value)
Incompatible with Zcd

FAQ

Is it always equivalent to a same-named 32-bit instruction?

Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.

Why do register restrictions matter?

Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.