Is it always equivalent to a same-named 32-bit instruction?
Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.
CM.PUSH
RISC-V CM.PUSH Instruction Details
Instruction ManualC-typeSave ra and s0-s11 to stack and adjust sp
Instruction Syntax
cm.push {reg_list}, -stack_adj
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
ZcmpStack & FunctionsCompressed Instruction
Instruction Behavior
CM.PUSH (Zcmp) pushes registers in {reg_list} (ra and up to 12 s-registers) to stack and decrements sp by stack_adj. stack_adj = stack_adj_base + spimm×16. Reuses c.fsdsp encoding, incompatible with Zcd. Stores may execute multiple times (fault recovery); sp adjustment commits atomically. Part of Zcmp, depends on Zca.
Quick Understanding & Search Notes
CM.PUSH is the 16-bit encoding form for compressed push multiple registers; its semantics and encodable register/immediate ranges must be read from the official Zc extension rules.
Compressed instructions often restrict register sets, immediate encodings, or destination registers; illegal combinations can be reserved.
Examples show assembly intent; actual encoding constraints follow the official C/Zc tables.
Common Usage Scenarios
Function Call & Return
Understand this scenario with real code like «cm.push {ra, s0-s5}, -64 # save ra,s0-s5, sp-=64».
Stack & Functions
Understand this scenario with real code like «cm.push {ra, s0-s5}, -64 # save ra,s0-s5, sp-=64».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is C-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Incompatible with Zcd (reuses c.fsdsp encoding)
Register list and stack adjustment constrained by encoding
Requires idempotent memory (stores may replay after faults)
No {ra, s0-s10} without s11 — must use {ra, s0-s11}
FAQ
Why do register restrictions matter?
Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.