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CM.POP

RISC-V CM.POP Instruction Details

Instruction ManualC2 (Zcmp CMPP)

Restore the ra and 0 to 12 s-registers selected by reg_list, then adjust sp

Instruction Syntax

cm.pop {reg_list}, stack_adj
Operand Breakdown
This is a C2 (Zcmp CMPP)-format instruction. Confirm operand positions based on the assembly syntax.
ZcmpStack & FunctionsCompressed Instruction
Related Search Terms
CM.POP instructionRISC-V CM.POPcm.pop syntaxcm.pop encodingcm.pop Zcmpcm.pop compressed instructioncompressed pop multiple registers

Instruction Behavior

CM.POP (Zcmp) pops registers in {reg_list} from stack and increments sp by stack_adj. Used with CM.PUSH. Note: CM.POP does NOT execute ret — only restores registers and deallocates stack frame. Reuses c.fsdsp encoding, incompatible with Zcd. Part of Zcmp, depends on Zca.

CM.POP Decode & Execute Animation

Shows only Zcmp architectural sequences and conditions; access order, grouping, or replay does not imply implementation detail.

cm.pop {reg_list}, stack_adj
Execution context

Zcmp depends on Zca and is incompatible with Zcd. Correct execution requires idempotent memory at sp; RV32E permits rlist=4-6 only.

sp <- 0x00001040
16-bit encoding fields
15..13
funct3
101
12..8
fixed
11010
7..4
rlist
0111
3..2
spimm
11
1..0
op
10
rlist=7 restores {ra, s0, s1, s2}; spimm=3 adds 48 bytes beyond stack_adj_base.
Pseudocode address mapping: s2 @ 0x0000103C; s1 @ 0x00001038; s0 @ 0x00001034; ra @ 0x00001030. The actual loads can occur in any order, be grouped, or repeat; sp' = 0x00001000 + 64 = 0x00001040.
sp <- 0x00001040
Architectural state has not been committed.

Quick Understanding & Search Notes

CM.POP is the 16-bit encoding form for compressed pop multiple registers; its semantics and encodable register/immediate ranges must be read from the official Zc extension rules.

Compressed instructions often restrict register sets, immediate encodings, or destination registers; illegal combinations can be reserved.
Examples show assembly intent; actual encoding constraints follow the official C/Zc tables.
RISC-V Unprivileged ISA Manual, Zc Extensions

Common Usage Scenarios

Function Call & Return

Understand this scenario with real code like «cm.pop {ra, s0-s5}, 64 # restore ra,s0-s5, sp+=64».

Immediates & Constants

Understand this scenario with real code like «cm.pop {ra, s0-s5}, 64 # restore ra,s0-s5, sp+=64».

Register Operations

Understand this scenario with real code like «cm.pop {ra, s0-s5}, 64 # restore ra,s0-s5, sp+=64».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is C2 (Zcmp CMPP).
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Incompatible with Zcd
CM.POP does NOT ret — only restores registers and deallocates frame
Register list and stack adjustment constrained by encoding

FAQ

Is it always equivalent to a same-named 32-bit instruction?

Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.

Why do register restrictions matter?

Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.