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CM.MVA01S

RISC-V CM.MVA01S Instruction Details

Instruction ManualC-type

Move two s0-s7 registers into a0 and a1 (may be the same)

Instruction Syntax

cm.mva01s r1s', r2s'
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
ZcmpStack & FunctionsCompressed Instruction
Related Search Terms
CM.MVA01S instructionRISC-V CM.MVA01Scm.mva01s syntaxcm.mva01s encodingcm.mva01s Zcmpcm.mva01s s0 a0

Instruction Behavior

CM.MVA01S (Zcmp) writes r1s' into a0 and r2s' into a1; the sources are UABI s0-s7. The two sources may be the same, and the two writes are atomically visible. On RV32E, encodings selecting s2-s7 for either specifier are reserved. It reuses c.fsdsp encodings, is incompatible with Zcd, and Zcmp depends on Zca.

CM.MVA01S Decode & Execute Animation

Shows only official compressed fields, conditions, and architectural state; it does not model a pipeline, cache, or timing.

cm.mva01s,
Execution context

Zcmp depends on Zca and is incompatible with Zcd; RV32E reserves s2-s7 specifiers.

a0 <- 0x11223344; a1 <- 0x55667788 (atomic)
16-bit encoding fields
15..13
funct3
101
12..10
fixed
011
9..7
r1s'
000
6..5
fixed
11
4..2
r2s'
001
1..0
op
10
Execution data path
The s-register specifiers restore s0 and s1 (encoded values 0 and 0).
a0 <- s0 (0x11223344); a1 <- s1 (0x55667788)
a0 <- 0x11223344; a1 <- 0x55667788 (atomic)
Architectural state has not been committed.

Quick Understanding & Search Notes

CM.MVA01S is a Zcmp 16-bit register-move instruction: two UABI s0-s7 sources, which may be the same, write a0/a1.

The official operation is X[10]=X[xreg1], X[11]=X[xreg2]; do not reverse it into a0/a1 -> saved registers.
r1s' and r2s' encode UABI s0-s7; RV32E selections of s2-s7 are reserved.
RISC-V Unprivileged ISA Manual, Zc Extensions

Common Usage Scenarios

Arrays & Memory Access

Understand this scenario with real code like «cm.mva01s s0, s1 # a0 = s0; a1 = s1».

Compressed & Code Size

Understand this scenario with real code like «cm.mva01s s0, s1 # a0 = s0; a1 = s1».

Function Call & Return

Understand this scenario with real code like «cm.mva01s s0, s1 # a0 = s0; a1 = s1».

Pre-Use Checklist

Syntax Check
  • Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
  • Confirm rd/rs1'/rs2' fields map to x8–x15.
Semantic Check
  • Note the limited operand space of compressed instructions.
  • Verify this compressed instruction has a corresponding 32-bit expansion.

Pitfalls / Common Confusions

r1s' and r2s' are source registers; the direction is s0-s7 -> a0/a1.
The two source registers must be UABI s0-s7; they may be the same.
RV32E encodings selecting s2-s7 are reserved, and both a-register writes are atomically visible.
Incompatible with Zcd.

FAQ

Is it always equivalent to a same-named 32-bit instruction?

Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.

Why do register restrictions matter?

Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.