May the two register specifiers be equal?
CM.MVA01S may use equal sources, giving a0/a1 the same old value; CM.MVSA01 requires different destinations.
CM.MVA01S
RISC-V CM.MVA01S Instruction Details
Instruction ManualC-typeMove two s0-s7 registers into a0 and a1 (may be the same)
Instruction Syntax
cm.mva01s r1s', r2s'
Operand Breakdown
RV32/RV64 Zcmp depends on Zca and conflicts with Zcd; 16-bit CMMV format.
The three-bit r1s'/r2s' fields encode UABI s0-s7: 0/1 select x8/x9 and 2-7 select x18-x23. RV32E selections s2-s7 are reserved.
r1s' → a0/x10 and r2s' → a1/x11; equal sources must share one old value.
Both XLEN-bit register writes are atomically visible; no data memory access, immediate, or direct single 32-bit equivalent encoding.
ZcmpStack & FunctionsCompressed Instruction
Instruction Behavior
CM.MVA01S (Zcmp) writes r1s' into a0 and r2s' into a1; the sources are UABI s0-s7. The two sources may be the same, and the two writes are atomically visible. On RV32E, encodings selecting s2-s7 for either specifier are reserved. It reuses c.fsdsp encodings, is incompatible with Zcd, and Zcmp depends on Zca.
CM.MVA01S Decode & Execute Animation
Shows only official compressed fields, conditions, and architectural state; it does not model a pipeline, cache, or timing.
cm.mva01s,
Execution context
Zcmp depends on Zca and is incompatible with Zcd; RV32E reserves s2-s7 specifiers.
cm.mva01s s0, s1 → a0 <- 0x11223344; a1 <- 0x55667788 (atomic)
16-bit encoding fields
15..13
funct3
101
12..10
fixed
011
9..7
r1s'
000
6..5
fixed
11
4..2
r2s'
001
1..0
op
10
Execution data path
The s-register specifiers restore s0 and s1 (encodings 000, 001 → x8, x9).
a0 <- s0 (0x11223344); a1 <- s1 (0x55667788)
a0 <- 0x11223344; a1 <- 0x55667788 (atomic)
Architectural state has not been committed.
Quick Understanding & Search Notes
CM.MVA01S is a Zcmp 16-bit register-move instruction: two UABI s0-s7 sources, which may be the same, write a0/a1.
The official operation is X[10]=X[xreg1], X[11]=X[xreg2]; do not reverse it into a0/a1 -> saved registers.
r1s' and r2s' encode UABI s0-s7; RV32E selections of s2-s7 are reserved.
Common Usage Scenarios
Register Operations
RV32/RV64 Zcmp, old s0=0x12 and s1=0x34: cm.mva01s s0, s1 atomically writes a0=0x12 and a1=0x34, leaving sources unchanged.
Compressed & Code Size
RV32/RV64 Zcmp, old s0=0x12 and s1=0x34: cm.mva01s s0, s1 atomically writes a0=0x12 and a1=0x34, leaving sources unchanged.
Pre-Use Checklist
Syntax Check
- RV32/RV64 Zcmp depends on Zca and conflicts with Zcd; 16-bit CMMV format.
- The three-bit r1s'/r2s' fields encode UABI s0-s7: 0/1 select x8/x9 and 2-7 select x18-x23. RV32E selections s2-s7 are reserved.
Semantic Check
- r1s' → a0/x10 and r2s' → a1/x11; equal sources must share one old value.
- Both XLEN-bit register writes are atomically visible; no data memory access, immediate, or direct single 32-bit equivalent encoding.
Pitfalls / Common Confusions
r1s' and r2s' are source registers; the direction is s0-s7 -> a0/a1.
The two source registers must be UABI s0-s7; they may be the same.
RV32E encodings selecting s2-s7 are reserved, and both a-register writes are atomically visible.
Incompatible with Zcd.
FAQ
Do these fields select x8-x15?
No. They encode UABI s0-s7: x8, x9, x18-x23. RV32E selections s2-s7 are reserved. Both register writes are atomically visible.