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CM.MVA01S

RISC-V CM.MVA01S Instruction Details

Instruction ManualC-type

Move two different s0-s7 registers into a0 and a1

Instruction Syntax

cm.mva01s r1s', r2s'
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
ZcmpStack & FunctionsCompressed Instruction
Related Search Terms
CM.MVA01S instructionRISC-V CM.MVA01Scm.mva01s syntaxcm.mva01s encodingcm.mva01s Zcmpcm.mva01s s0 a0

Instruction Behavior

CM.MVA01S (Zcmp) writes r1s' into a0 and r2s' into a1; both source registers are from s0-s7 and must be different. It is used to move values from saved registers into a0/a1. The instruction reuses c.fsdsp encodings, is incompatible with Zcd, belongs to Zcmp, and depends on Zca.

Quick Understanding & Search Notes

CM.MVA01S is a Zcmp 16-bit register-move instruction whose direction is from two different s0-s7 source registers into a0/a1.

The official operation is X[10]=X[xreg1], X[11]=X[xreg2]; do not reverse it into a0/a1 -> saved registers.
r1s' and r2s' must be different, and the encoding covers only s0-s7.
RISC-V Unprivileged ISA Manual, Zc Extensions

Common Usage Scenarios

Arrays & Memory Access

Understand this scenario with real code like «cm.mva01s s0, s1 # a0 = s0; a1 = s1».

Compressed & Code Size

Understand this scenario with real code like «cm.mva01s s0, s1 # a0 = s0; a1 = s1».

Function Call & Return

Understand this scenario with real code like «cm.mva01s s0, s1 # a0 = s0; a1 = s1».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is C-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

r1s' and r2s' are source registers; the direction is s0-s7 -> a0/a1.
The two source registers must be different and must come from s0-s7.
Incompatible with Zcd.

FAQ

Is it always equivalent to a same-named 32-bit instruction?

Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.

Why do register restrictions matter?

Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.