When does rm matter for fcvt.h.l?
When the integer value cannot be exactly represented in the destination floating-point format, rm or dynamic frm selects the rounding direction.
FCVT.H.L
RISC-V FCVT.H.L Instruction Details
Instruction ManualR-typeConvert a signed 64-bit integer to half-precision floating point [RV64]; rm or dynamic frm selects rounding when needed.
Instruction Syntax
fcvt.h.l rd, rs1, rm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZfhFloating-Point Convert
Instruction Behavior
fcvt.h.l converts a signed 64-bit integer source to a half-precision floating-point result. If the value is not exactly representable, the result is rounded according to rm and written to f[rd].
FCVT.H.L Decode And Execute Animation
Shows the Zfh-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, the rm rounding field, read the integer source, then write the floating-point destination.
rd
rs1
rm
fcvt.h.l
,
,
Execution Context
fmt=H (10)
rs2=L
rounding: RNE nearest-even
fflags: NX
RV64-only
31..27
26..25
24..20
19..15
14..12
11..7
6..0
11010
FCVT.H
10
fmt=H
00010
rs2=L
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xD4258553
opcode
1010011 -> OP-FP
funct5/fmt
11010 + 10 -> FCVT.H.L
rs2
00010 -> L source
rm
000 -> RNE nearest-even
rd/rs1
fa0(f10) / a1(x11)
read
a1(x11) = -2049
convert
int64 -2049 -> H -2048.0
write
fa0(f10) = -2048.0; NX
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FCVT uses opcode 1010011.
encoding: 0xD4258553
syntax : fcvt.h.l fa0(f10), a1(x11), rne
result : fa0(f10) = -2048.0; NX
The current 64-bit integer example is not exactly representable as H format, so the rounded example shows NX.
FCVT Conversion View
L source
-2049
conversion
int64 -2049 -> H -2048.0
writeback
fa0(f10) = -2048.0
The current 64-bit integer example is not exactly representable as H format, so the rounded example shows NX.
This animation shows only Zfh-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.
Quick Understanding & Search Notes
fcvt.h.l converts a signed 64-bit integer source to a half-precision floating-point result. If the value is not exactly representable, the result is rounded according to rm and written to f[rd].
OP-FP opcode is 1010011; funct5=11010 denotes integer-to-FP FCVT and fmt=10 denotes an H destination.
rs2=00010 selects the L signed 64-bit integer source; rs1 is an integer register and rd is an FP register.
L/LU 64-bit integer source forms are RV64-only.
The integer source operand comes from x[rs1], not a floating-point register, so there is no source NaN-boxing requirement.
The floating-point result is NaN-boxed in wider FLEN registers according to the destination format.
NX is set when rounding changes the result; half-precision range overflow also sets OF. rm=111 uses frm and reserved rm encodings are not normal animation input.
Common Usage Scenarios
Floating Point Basic
Understand this scenario with real code like «fcvt.h.l f0, x10, rne # f0 = (half)(long)x10 (RV64)».
Numerical Computing
Understand this scenario with real code like «fcvt.h.l f0, x10, rne # f0 = (half)(long)x10 (RV64)».
Pre-Use Checklist
Syntax Check
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
Semantic Check
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.
Pitfalls / Common Confusions
L/LU 64-bit integer source forms are RV64-only.
The integer source operand comes from x[rs1], not a floating-point register, so there is no source NaN-boxing requirement.
The floating-point result is NaN-boxed in wider FLEN registers according to the destination format.
If the rounded result differs from the integer source, the conversion sets NX; half-precision range overflow also sets OF. rm=111 uses frm, and reserved rounding encodings have reserved behavior.
FAQ
How does fcvt.h.l differ from related FCVT instructions?
It differs by source/destination format, integer signedness, RV64 restriction, and whether rm/frm rounding is needed; this form sets NX when rounding changes the result and OF on half-precision range overflow.