When does rm matter for fcvt.h.l?
When the integer value cannot be exactly represented in the destination floating-point format, rm or dynamic frm selects the rounding direction.
FCVT.H.L
RISC-V FCVT.H.L Instruction Details
Instruction ManualR-typeConvert signed 64-bit int to half FP [RV64]. R-type, fmt=H(10). Large ints lose precision.
Instruction Syntax
fcvt.h.l rd, rs1, rm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZfhFloating-Point Convert
Instruction Behavior
fcvt.h.l converts a signed 64-bit integer source to a half-precision floating-point result. If the value is not exactly representable, the result is rounded according to rm and written to f[rd].
Quick Understanding & Search Notes
fcvt.h.l converts a signed 64-bit integer source to a half-precision floating-point result. If the value is not exactly representable, the result is rounded according to rm and written to f[rd].
The rs2/fmt encoding selects source and destination formats; the mnemonic suffixes carry the main semantic distinction.
L/LU 64-bit integer source forms are RV64-only.
The integer source operand comes from x[rs1], not a floating-point register, so there is no source NaN-boxing requirement.
The floating-point result is NaN-boxed in wider FLEN registers according to the destination format.
Common Usage Scenarios
Floating Point Basic
Understand this scenario with real code like «fcvt.h.l f0, x10, rne # f0 = (half)(long)x10 (RV64)».
Numerical Computing
Understand this scenario with real code like «fcvt.h.l f0, x10, rne # f0 = (half)(long)x10 (RV64)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
L/LU 64-bit integer source forms are RV64-only.
The integer source operand comes from x[rs1], not a floating-point register, so there is no source NaN-boxing requirement.
The floating-point result is NaN-boxed in wider FLEN registers according to the destination format.
FAQ
How does fcvt.h.l differ from related FCVT instructions?
It differs by source/destination format, integer signedness, RV64 restrictions, and whether rounding or invalid conversion can occur.