When does rm matter for fcvt.h.lu?
When the integer value cannot be exactly represented in the destination floating-point format, rm or dynamic frm selects the rounding direction.
FCVT.H.LU
RISC-V FCVT.H.LU Instruction Details
Instruction ManualR-typeConvert an unsigned 64-bit integer to half-precision floating point [RV64]; rm or dynamic frm selects rounding when needed.
Instruction Syntax
fcvt.h.lu rd, rs1, rm
rd selects f0–f31; rs1 selects integer x0–x31 (x0 is always zero); rs2 selects format LU, not a second source register.
32-bit OP-FP: funct5=11010, fmt=10, rs2=00011, opcode=1010011; no immediate.
Requires RV64 Zfh; rm/frm controls conversion of a 64-bit integer to H. Optional rm defaults to dyn; reserved rounding encodings remain reserved.
Enable required extensions and FP state. Check FP-source NaN-boxing when narrower than FLEN; a narrower destination gets upper ones. Applicable exceptions accrue in fflags; setting a flag does not itself cause an FP exception trap.
ZfhFloating-Point Convert
Instruction Behavior
fcvt.h.lu converts an unsigned 64-bit integer from x[rs1] to half precision in f[rd] on RV64. Inexact values round according to rm or dynamic frm.
FCVT.H.LU Decode And Execute Animation
Shows the Zfh-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, the rm rounding field, read the integer source, then write the floating-point destination.
rd
rs1
rm
fcvt.h.lu
,
,
Leave rm empty for the assembly default dyn (111); this DYN example fixes frm=RNE. Use lowercase rne/rtz/rdn/rup/rmm/dyn only.
Execution Context
fmt=H (10)
rs2=LU
rounding: RNE nearest-even
fflags: NX
RV64-only
Assume required extensions and FP state are enabled, applicable source NaN-boxing is valid, and initial fflags=0. Results preview the current input; Writeback represents commit.
31..27
26..25
24..20
19..15
14..12
11..7
6..0
11010
FCVT.H
10
fmt=H
00011
rs2=LU
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xD4358553
opcode
1010011 -> OP-FP
funct5/fmt
11010 + 10 -> FCVT.H.LU
rs2
00011 -> LU source
rm
000 -> RNE nearest-even
rd/rs1
fa0(f10) / a1(x11)
read
a1(x11) = 4097
convert
uint64 4097 -> H 4096.0
write
fa0(f10) = 4096.0; NX
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FCVT uses opcode 1010011.
encoding: 0xD4358553
syntax : fcvt.h.lu fa0(f10), a1(x11), rne
result : fa0(f10) = 4096.0; NX
The current 64-bit integer example is not exactly representable as H format, so the rounded example shows NX.
FCVT Conversion View
LU source
4097
conversion
uint64 4097 -> H 4096.0
writeback
fa0(f10) = 4096.0
The current 64-bit integer example is not exactly representable as H format, so the rounded example shows NX.
This animation shows only Zfh-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.
Quick Understanding & Search Notes
fcvt.h.lu reads an unsigned 64-bit integer from x[rs1], rounds to half precision according to rm or dynamic frm when needed, and writes f[rd]; this form is RV64-only.
OP-FP opcode is 1010011; funct5=11010 denotes integer-to-FP FCVT and fmt=10 denotes an H destination.
rs2=00011 selects the LU unsigned 64-bit integer source; rs1 is an integer register and rd is an FP register.
L/LU 64-bit integer source forms are RV64-only.
The integer source operand comes from x[rs1], not a floating-point register, so there is no source NaN-boxing requirement.
The floating-point result is NaN-boxed in wider FLEN registers according to the destination format.
NX is set when rounding changes the result; half-precision range overflow also sets OF. rm=111 uses frm and reserved rm encodings are not normal animation input.
An optional lowercase rm operand defaults to dyn (rm=111), which uses current frm; reserved rounding encodings have reserved behavior.
Examples assume required extensions and FP state are enabled and initial fflags=0. Exception flags accrue; setting a flag does not itself cause an FP exception trap.
Zfh integer conversions are not included in Zfhmin; x0 always reads 0. 65504 converts exactly; RNE rounds 2049 to 2048 and sets NX.
Common Usage Scenarios
Integer-to-FP conversion
Understand this scenario with real code like «fcvt.h.lu f0, x10, rne # 2049 -> 2048, NX; RV64, initial x10=2049, fflags=0».
Pre-Use Checklist
Syntax Check
- rd selects f0–f31; rs1 selects integer x0–x31 (x0 is always zero); rs2 selects format LU, not a second source register.
- 32-bit OP-FP: funct5=11010, fmt=10, rs2=00011, opcode=1010011; no immediate.
Semantic Check
- Requires RV64 Zfh; rm/frm controls conversion of a 64-bit integer to H. Optional rm defaults to dyn; reserved rounding encodings remain reserved.
- Enable required extensions and FP state. Check FP-source NaN-boxing when narrower than FLEN; a narrower destination gets upper ones. Applicable exceptions accrue in fflags; setting a flag does not itself cause an FP exception trap.
Pitfalls / Common Confusions
L/LU 64-bit integer source forms are RV64-only.
The integer source operand comes from x[rs1], not a floating-point register, so there is no source NaN-boxing requirement.
The floating-point result is NaN-boxed in wider FLEN registers according to the destination format.
If the rounded result differs from the integer source, the conversion sets NX; half-precision range overflow also sets OF. rm=111 uses frm, and reserved rounding encodings have reserved behavior.
FAQ
How does fcvt.h.lu differ from related FCVT instructions?
It differs by source/destination format, integer signedness, RV64 restriction, and whether rm/frm rounding is needed; this form sets NX when rounding changes the result and OF on half-precision range overflow.