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FCVT.H.W

RISC-V FCVT.H.W Instruction Details

Instruction ManualR-type

Convert signed 32-bit integer to half-precision float

Instruction Syntax

fcvt.h.w rd, rs1, rm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZfhFloating-Point Convert
Related Search Terms
fcvt.h.w instructionsigned 32-bit integer to half-precisionfcvt.h.w conversionfcvt.h.w roundingfcvt.h.w floating point

Instruction Behavior

fcvt.h.w converts a signed 32-bit integer source to a half-precision floating-point result. If the value is not exactly representable, the result is rounded according to rm and written to f[rd].

Quick Understanding & Search Notes

fcvt.h.w converts a signed 32-bit integer source to a half-precision floating-point result. If the value is not exactly representable, the result is rounded according to rm and written to f[rd].

The rs2/fmt encoding selects source and destination formats; the mnemonic suffixes carry the main semantic distinction.
W/WU forms read a 32-bit signed or unsigned integer source value.
The integer source operand comes from x[rs1], not a floating-point register, so there is no source NaN-boxing requirement.
The floating-point result is NaN-boxed in wider FLEN registers according to the destination format.
RISC-V Unprivileged ISA Manual, Zfh half-precision floating-point extension

Common Usage Scenarios

Type Conversion

Understand this scenario with real code like «fcvt.h.w f10, x11, rne ; f10 = (half)x11».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

W/WU forms read a 32-bit signed or unsigned integer source value.
The integer source operand comes from x[rs1], not a floating-point register, so there is no source NaN-boxing requirement.
The floating-point result is NaN-boxed in wider FLEN registers according to the destination format.

FAQ

When does rm matter for fcvt.h.w?

When the integer value cannot be exactly represented in the destination floating-point format, rm or dynamic frm selects the rounding direction.

How does fcvt.h.w differ from related FCVT instructions?

It differs by source/destination format, integer signedness, RV64 restrictions, and whether rounding or invalid conversion can occur.