FCVT.H.WU

RISC-V FCVT.H.WU Instruction Details

Instruction ManualR-type

Convert an unsigned 32-bit integer to half-precision FP, rounding according to rm or frm.

Instruction Syntax

fcvt.h.wu rd, rs1, rm

Operand Breakdown

rd: destination half-precision FP register; rs1: source unsigned 32-bit integer register.

rm: rounding-mode operand; rm=111 uses frm. Encoded funct5=11010 and fmt=10 select target H, while rs2=00001 selects unsigned WU integer source.

rs2 selects integer source width and signedness, not a second assembly source register; integer-to-H conversion rounds according to rm/frm.

ZfhFloating-Point Convert

Related Search Terms

fcvt.h.wu instruction unsigned 32-bit integer to half-precision fcvt.h.wu conversion fcvt.h.wu rounding fcvt.h.wu floating point

Instruction Behavior

fcvt.h.wu converts the unsigned 32-bit integer in x[rs1] to a half-precision result in f[rd]. Its OP-FP encoding uses funct5=11010, fmt=H (10), and rs2=WU (00001); an inexact result rounds according to rm or dynamic frm and records applicable fflags.

FCVT.H.WU Decode And Execute Animation

Shows the Zfh-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, the rm rounding field, read the integer source, then write the floating-point destination.

rs1

fcvt.h.wu

Execution Context

fmt=H (10)

rs2=WU

rounding: RNE nearest-even

fflags: OF|NX

a1(x11) source valueEnter a 32-bit integer or 0x hex; half-precision overflow examples show the rm-selected result and OF|NX

31..27

26..25

24..20

19..15

14..12

11..7

6..0

11010

FCVT.H

fmt=H

00001

rs2=WU

01011

rs1

000

01010

1010011

OP-FP

Execution Data Path

instruction

0xD4158553

opcode

1010011 -> OP-FP

funct5/fmt

11010 + 10 -> FCVT.H.WU

rs2

00001 -> WU source

000 -> RNE nearest-even

rd/rs1

fa0(f10) / a1(x11)

read

a1(x11) = 4294967295

convert

uint32 4294967295 -> H +inf

write

fa0(f10) = +inf; OF|NX

Current Step

Fetch: show the 32-bit OP-FP encoding

The word is split as an R-type OP-FP instruction; FCVT uses opcode 1010011.

encoding: 0xD4158553

syntax : fcvt.h.wu fa0(f10), a1(x11), rne

result : fa0(f10) = +inf; OF|NX

The current 32-bit integer example overflows the half-precision finite range; rm selects infinity or the same-sign maximum finite value, and the example sets OF|NX.

FCVT Conversion View

WU source

4294967295

conversion

uint32 4294967295 -> H +inf

writeback

fa0(f10) = +inf

The current 32-bit integer example overflows the half-precision finite range; rm selects infinity or the same-sign maximum finite value, and the example sets OF|NX.

This animation shows only Zfh-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.

Quick Understanding & Search Notes

fcvt.h.wu converts an unsigned 32-bit integer source to a half-precision floating-point result. If the value is not exactly representable, the result is rounded according to rm and written to f[rd].

OP-FP funct5=11010, fmt=H (10), and rs2=WU (00001) select FCVT.H.WU; rs2 is an integer width/signedness selector, not a register operand.

W/WU forms read a 32-bit signed or unsigned integer source value.

The integer source operand comes from x[rs1], not a floating-point register, so there is no source NaN-boxing requirement.

The floating-point result is NaN-boxed in wider FLEN registers according to the destination format.

RISC-V Unprivileged ISA Manual, Zfh half-precision floating-point extension

Common Usage Scenarios

Integer-to-Floating-Point Conversion

Understand this scenario with real code like «fcvt.h.wu f0, x10, rne # f0 = (half)(unsigned)x10».

Pre-Use Checklist

Syntax Check

Verify rd, rs1, rs2 (and rs3) are valid GPRs.
Confirm funct3 and funct7 encoding is correct.

Semantic Check

Check if the result affects subsequent branches or address calculations.
Ensure the rd register is not overwritten by another instruction.

Pitfalls / Common Confusions