When does rm matter for fcvt.h.wu?
When the integer value cannot be exactly represented in the destination floating-point format, rm or dynamic frm selects the rounding direction.
FCVT.H.WU
RISC-V FCVT.H.WU Instruction Details
Instruction ManualR-typeConvert an unsigned 32-bit integer to half-precision FP, rounding according to rm or frm.
Instruction Syntax
fcvt.h.wu rd, rs1, rm
rd selects FP f0–f31, including writable f0; rs1 selects integer x0–x31, reading the low 32 bits with x0 always zero; rs2 is a format selector, not a second source register.
32-bit OP-FP: funct5=11010, fmt=10, rs2=00001, opcode=1010011; no immediate.
RV32/RV64 Zfh; enable required extensions and FP state. Optional rm defaults to dyn, using frm; static 101/110 and dynamic frm=101–111 have reserved behavior.
Integer sources need no NaN-boxing. An H result gets upper ones when FLEN>16. Applicable exceptions accrue in fflags; setting a flag does not itself cause an FP trap.
ZfhFloating-Point Convert
Instruction Behavior
fcvt.h.wu converts the unsigned 32-bit integer in x[rs1] to a half-precision result in f[rd]. Its OP-FP encoding uses funct5=11010, fmt=H (10), and rs2=WU (00001); an inexact result rounds according to rm or dynamic frm and records applicable fflags.
FCVT.H.WU Decode And Execute Animation
Shows the Zfh-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, the rm rounding field, read the integer source, then write the floating-point destination.
rd
rs1
rm
fcvt.h.wu
,
,
Leave rm empty for the assembly default dyn (111); this DYN example fixes frm=RNE. Use lowercase rne/rtz/rdn/rup/rmm/dyn only.
Execution Context
fmt=H (10)
rs2=WU
rounding: RNE nearest-even
fflags: OF|NX
Assume required extensions and FP state are enabled, applicable source NaN-boxing is valid, and initial fflags=0. Results preview the current input; Writeback represents commit.
31..27
26..25
24..20
19..15
14..12
11..7
6..0
11010
FCVT.H
10
fmt=H
00001
rs2=WU
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xD4158553
opcode
1010011 -> OP-FP
funct5/fmt
11010 + 10 -> FCVT.H.WU
rs2
00001 -> WU source
rm
000 -> RNE nearest-even
rd/rs1
fa0(f10) / a1(x11)
read
a1(x11) = 4294967295
convert
uint32 4294967295 -> H +inf
write
fa0(f10) = +inf; OF|NX
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FCVT uses opcode 1010011.
encoding: 0xD4158553
syntax : fcvt.h.wu f10, x11, rne
result : fa0(f10) = +inf; OF|NX
The current 32-bit integer example overflows the half-precision finite range; rm selects infinity or the same-sign maximum finite value, and the example sets OF|NX.
FCVT Conversion View
WU source
4294967295
conversion
uint32 4294967295 -> H +inf
writeback
fa0(f10) = +inf
The current 32-bit integer example overflows the half-precision finite range; rm selects infinity or the same-sign maximum finite value, and the example sets OF|NX.
This animation shows only Zfh-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.
Quick Understanding & Search Notes
fcvt.h.wu converts an unsigned 32-bit integer source to a half-precision floating-point result. If the value is not exactly representable, the result is rounded according to rm and written to f[rd].
OP-FP funct5=11010, fmt=H (10), and rs2=WU (00001) select FCVT.H.WU; rs2 is an integer width/signedness selector, not a register operand.
Read the low 32 bits of x[rs1] as an unsigned integer; the upper 32 bits on RV64 do not participate. rs1=x0 reads 0.
The integer source operand comes from x[rs1], not a floating-point register, so there is no source NaN-boxing requirement.
The floating-point result is NaN-boxed in wider FLEN registers according to the destination format.
Omitting rm defaults to dyn (111), selecting frm; static 101/110 and dynamic frm=101–111 are reserved. fflags accrues exceptions; setting a flag does not itself generate an FP trap.
Common Usage Scenarios
Integer-to-Floating-Point Conversion
Understand this scenario with real code like «fcvt.h.wu f10, x11, rne # f10 = 4096; NX; Zfh/FP state enabled; x11 = 4097».
Pre-Use Checklist
Syntax Check
- rd selects FP f0–f31, including writable f0; rs1 selects integer x0–x31, reading the low 32 bits with x0 always zero; rs2 is a format selector, not a second source register.
- 32-bit OP-FP: funct5=11010, fmt=10, rs2=00001, opcode=1010011; no immediate.
Semantic Check
- RV32/RV64 Zfh; enable required extensions and FP state. Optional rm defaults to dyn, using frm; static 101/110 and dynamic frm=101–111 have reserved behavior.
- Integer sources need no NaN-boxing. An H result gets upper ones when FLEN>16. Applicable exceptions accrue in fflags; setting a flag does not itself cause an FP trap.
Pitfalls / Common Confusions
Read the low 32 bits of x[rs1] as an unsigned integer; the upper 32 bits on RV64 do not participate. rs1=x0 reads 0.
The integer source operand comes from x[rs1], not a floating-point register, so there is no source NaN-boxing requirement.
The floating-point result is NaN-boxed in wider FLEN registers according to the destination format.
FAQ
What if the integer is not exactly representable in half precision?
Round according to rm/frm and set NX. Overflow produces a signed infinity or maximum finite value according to the rounding direction and sets OF|NX. The H result is NaN-boxed.