FCVT.L.H

RISC-V FCVT.L.H Instruction Details

Instruction ManualR-type

Convert half-precision FP to a signed 64-bit integer [RV64], rounding according to rm or frm.

Instruction Syntax

fcvt.l.h rd, rs1, rm

Operand Breakdown

rd: destination signed 64-bit integer register (RV64-only); rs1: source half-precision FP register.

rm: rounding-mode operand; rm=111 uses frm. Encoded funct5=11000 and fmt=10 select source H, while rs2=00010 selects signed L integer target.

rs2 selects integer target width and signedness, not a second assembly source register; H-to-L conversion rounds according to rm/frm.

ZfhFloating-Point Convert

Related Search Terms

fcvt.l.h instruction half-precision to signed 64-bit integer fcvt.l.h conversion fcvt.l.h rounding fcvt.l.h floating point

Instruction Behavior

On RV64, fcvt.l.h converts the half-precision value in f[rs1] to a signed 64-bit integer in x[rd]. Its OP-FP encoding uses funct5=11000, fmt=H (10), and rs2=L (00010), then rounds according to rm or dynamic frm. An out-of-range value, infinity, or NaN follows the official invalid-conversion endpoint rule and sets NV.

FCVT.L.H Decode And Execute Animation

Shows the Zfh-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, the rm rounding field, read the floating-point source, then write the integer destination.

rs1

fcvt.l.h

Execution Context

fmt=H (10)

rs2=L

rounding: RNE nearest-even

fflags: NX

RV64-only

fa1(f11) source valueEnter a finite exact example: 0, 1, -1, 1.25, -1.5, 2, 3.5, 9; special-value paths are covered in static text

31..27

26..25

24..20

19..15

14..12

11..7

6..0

11000

FCVT.L

fmt=H

00010

rs2=L

01011

rs1

000

01010

1010011

OP-FP

Execution Data Path

instruction

0xC4258553

opcode

1010011 -> OP-FP

funct5/fmt

11000 + 10 -> FCVT.L.H

rs2

00010 -> L target

000 -> RNE nearest-even

rd/rs1

a0(x10) / fa1(f11)

read

fa1(f11) = -42.75

convert

-42.75 -> int64 -43

write

a0(x10) = -43; NX

Current Step

Fetch: show the 32-bit OP-FP encoding

The word is split as an R-type OP-FP instruction; FCVT uses opcode 1010011.

encoding: 0xC4258553

syntax : fcvt.l.h a0(x10), fa1(f11), rne

result : a0(x10) = -43; NX

The current example rounds to a 64-bit integer according to rm and shows NX because the source has a fractional part.

FCVT Conversion View

H FP source

-42.75

conversion

-42.75 -> int64 -43

writeback

a0(x10) = -43

The current example rounds to a 64-bit integer according to rm and shows NX because the source has a fractional part.

This animation shows only Zfh-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.

Quick Understanding & Search Notes

fcvt.l.h converts a half-precision source operand to a signed 64-bit integer result. Floating-point-to-integer conversion rounds according to rm and writes integer register rd.

OP-FP funct5=11000, fmt=H (10), and rs2=L (00010) select FCVT.L.H: fmt is the half-precision source format and rs2 selects the signed 64-bit integer destination.

L/LU 64-bit integer result forms are RV64-only.

Out-of-range integer targets or NaN inputs follow the official invalid floating-point-to-integer conversion rules and set NV.

Floating-point source operands in wider FLEN registers must satisfy NaN-boxing rules.

RISC-V Unprivileged ISA Manual, Zfh half-precision floating-point extension

Common Usage Scenarios

Floating-Point-to-Integer Conversion

Understand this scenario with real code like «fcvt.l.h x10, f0, rtz # x10 = (long)f0 (RV64)».

Pre-Use Checklist

Syntax Check

Verify rd, rs1, rs2 (and rs3) are valid GPRs.
Confirm funct3 and funct7 encoding is correct.

Semantic Check

Check if the result affects subsequent branches or address calculations.
Ensure the rd register is not overwritten by another instruction.

Pitfalls / Common Confusions