When does rm matter for fcvt.l.h?
When conversion requires rounding, rm or dynamic frm selects the rounding direction; out-of-range or NaN inputs follow the official invalid-conversion rule.
FCVT.L.H
RISC-V FCVT.L.H Instruction Details
Instruction ManualR-typeConvert half-precision FP to a signed 64-bit integer [RV64], rounding according to rm or frm.
Instruction Syntax
fcvt.l.h rd, rs1, rm
rd selects integer x0–x31, with x0 discarding results; rs1 selects FP f0–f31; rs2 is a format selector, not a second source register.
32-bit OP-FP: funct5=11000, fmt=10, rs2=00010, opcode=1010011; no immediate.
RV64 Zfh only; enable required extensions and FP state. Optional rm defaults to dyn, using frm; static 101/110 and dynamic frm=101–111 have reserved behavior.
FP sources narrower than FLEN require NaN-boxing checks; an invalid box is treated as a canonical source-format NaN. Integer results need no NaN-boxing. Applicable exceptions accrue in fflags; setting a flag does not itself cause an FP trap.
ZfhFloating-Point Convert
Instruction Behavior
On RV64, fcvt.l.h converts the half-precision value in f[rs1] to a signed 64-bit integer in x[rd]. Its OP-FP encoding uses funct5=11000, fmt=H (10), and rs2=L (00010), then rounds according to rm or dynamic frm. An out-of-range value, infinity, or NaN follows the official invalid-conversion endpoint rule and sets NV.
FCVT.L.H Decode And Execute Animation
Shows the Zfh-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, the rm rounding field, read the floating-point source, then write the integer destination.
rd
rs1
rm
fcvt.l.h
,
,
Leave rm empty for the assembly default dyn (111); this DYN example fixes frm=RNE. Use lowercase rne/rtz/rdn/rup/rmm/dyn only.
Execution Context
fmt=H (10)
rs2=L
rounding: RNE nearest-even
fflags: NX
RV64-only
Assume required extensions and FP state are enabled, applicable source NaN-boxing is valid, and initial fflags=0. Results preview the current input; Writeback represents commit.
31..27
26..25
24..20
19..15
14..12
11..7
6..0
11000
FCVT.L
10
fmt=H
00010
rs2=L
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xC4258553
opcode
1010011 -> OP-FP
funct5/fmt
11000 + 10 -> FCVT.L.H
rs2
00010 -> L target
rm
000 -> RNE nearest-even
rd/rs1
a0(x10) / fa1(f11)
read
fa1(f11) = -42.75
convert
-42.75 -> int64 -43
write
a0(x10) = -43; NX
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FCVT uses opcode 1010011.
encoding: 0xC4258553
syntax : fcvt.l.h x10, f11, rne
result : a0(x10) = -43; NX
The current example rounds to a 64-bit integer according to rm and shows NX because the source has a fractional part.
FCVT Conversion View
H FP source
-42.75
conversion
-42.75 -> int64 -43
writeback
a0(x10) = -43
The current example rounds to a 64-bit integer according to rm and shows NX because the source has a fractional part.
This animation shows only Zfh-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.
Quick Understanding & Search Notes
On RV64, fcvt.l.h rounds the half-precision value in f[rs1] to a signed 64-bit integer according to rm or dynamic frm, then writes x[rd].
OP-FP funct5=11000, fmt=H (10), and rs2=L (00010) select FCVT.L.H: fmt is the half-precision source format and rs2 selects the signed 64-bit integer destination.
L/LU 64-bit integer result forms are RV64-only.
−∞ writes −2^63; +∞ or NaN writes 2^63−1, setting NV without NX. All finite H values fit int64; fractional conversions set NX. With rd=x0 the integer result is discarded, while exception flags can still accrue.
When FLEN>16, all upper source bits must be 1; otherwise the source is treated as a half-precision canonical NaN.
Omitting rm defaults to dyn (111), selecting frm; static 101/110 and dynamic frm=101–111 are reserved. fflags accrues exceptions; setting a flag does not itself generate an FP trap.
Common Usage Scenarios
Floating-Point-to-Integer Conversion
Understand this scenario with real code like «fcvt.l.h x10, f0, rtz # x10 = -42; NX; RV64, Zfh/FP state enabled; f0 holds H value -42.75».
Pre-Use Checklist
Syntax Check
- rd selects integer x0–x31, with x0 discarding results; rs1 selects FP f0–f31; rs2 is a format selector, not a second source register.
- 32-bit OP-FP: funct5=11000, fmt=10, rs2=00010, opcode=1010011; no immediate.
Semantic Check
- RV64 Zfh only; enable required extensions and FP state. Optional rm defaults to dyn, using frm; static 101/110 and dynamic frm=101–111 have reserved behavior.
- FP sources narrower than FLEN require NaN-boxing checks; an invalid box is treated as a canonical source-format NaN. Integer results need no NaN-boxing. Applicable exceptions accrue in fflags; setting a flag does not itself cause an FP trap.
Pitfalls / Common Confusions
L/LU 64-bit integer result forms are RV64-only.
−∞ writes −2^63; +∞ or NaN writes 2^63−1, setting NV without NX. All finite H values fit int64; fractional conversions set NX. With rd=x0 the integer result is discarded, while exception flags can still accrue.
When FLEN>16, all upper source bits must be 1; otherwise the source is treated as a half-precision canonical NaN.
FAQ
How does fcvt.l.h differ from related FCVT instructions?
It differs by source/destination format, integer signedness, RV64 restrictions, and whether rounding or invalid conversion can occur.