When does rm matter for fcvt.l.q?
When conversion requires rounding, rm or dynamic frm selects the rounding direction; out-of-range or NaN inputs follow the official invalid-conversion rule.
FCVT.L.Q
RISC-V FCVT.L.Q Instruction Details
Instruction ManualR-typeConvert quad FP to signed 64-bit int [RV64]. In OP-FP R-type fields, fmt=Q (11) encodes the FP source format and rs2=L (00010) encodes the signed 64-bit integer target.
Instruction Syntax
fcvt.l.q rd, rs1, rm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
QFloating-Point Convert
Instruction Behavior
fcvt.l.q converts a quad-precision source operand to a signed 64-bit integer result. Floating-point-to-integer conversion rounds according to rm and writes integer register rd.
FCVT.L.Q Decode And Execute Animation
Shows the Q-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, the rm rounding field, read the floating-point source, then write the integer destination.
rd
rs1
rm
fcvt.l.q
,
,
Execution Context
fmt=Q (11)
rs2=L
rounding: RNE nearest-even
fflags: NX
RV64-only
The source value is invalid and is not used for execution. The animation is using a legal FCVT.L.Q default example value.
31..27
26..25
24..20
19..15
14..12
11..7
6..0
11000
FCVT.L
11
fmt=Q
00010
rs2=L
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xC6258553
opcode
1010011 -> OP-FP
funct5/fmt
11000 + 11 -> FCVT.L.Q
rs2
00010 -> L target
rm
000 -> RNE nearest-even
rd/rs1
a0(x10) / fa1(f11)
read
fa1(f11) = -42.75
convert
-42.75 -> int64 -43
write
a0(x10) = -43; NX
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FCVT uses opcode 1010011.
encoding: 0xC6258553
syntax : fcvt.l.q a0(x10), fa1(f11), rne
result : a0(x10) = -43; NX
The current example rounds to a 64-bit integer according to rm and shows NX because the source has a fractional part.
FCVT Conversion View
Q FP source
-42.75
conversion
-42.75 -> int64 -43
writeback
a0(x10) = -43
The current example rounds to a 64-bit integer according to rm and shows NX because the source has a fractional part.
This animation shows only Q-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.
Quick Understanding & Search Notes
fcvt.l.q converts a quad-precision source operand to a signed 64-bit integer result. Floating-point-to-integer conversion rounds according to rm and writes integer register rd.
The rs2/fmt encoding selects source and destination formats; the mnemonic suffixes carry the main semantic distinction.
L/LU 64-bit integer result forms are RV64-only.
Out-of-range integer targets or NaN inputs follow the official invalid floating-point-to-integer conversion rules and set NV.
Floating-point source operands in wider FLEN registers must satisfy NaN-boxing rules.
Common Usage Scenarios
Floating Point Basic
Understand this scenario with real code like «fcvt.l.q x10, f0, rtz # x10 = (long)f0 (RV64)».
Numerical Computing
Understand this scenario with real code like «fcvt.l.q x10, f0, rtz # x10 = (long)f0 (RV64)».
Pre-Use Checklist
Syntax Check
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
Semantic Check
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.
Pitfalls / Common Confusions
L/LU 64-bit integer result forms are RV64-only.
Out-of-range integer targets or NaN inputs follow the official invalid floating-point-to-integer conversion rules and set NV.
Floating-point source operands in wider FLEN registers must satisfy NaN-boxing rules.
FAQ
How does fcvt.l.q differ from related FCVT instructions?
It differs by source/destination format, integer signedness, RV64 restrictions, and whether rounding or invalid conversion can occur.