Does every negative input set NV?
No. Range is checked after rounding: -0.5 under RNE or RTZ becomes 0 with NX, while RDN produces an out-of-range −1 and sets NV.
FCVT.WU.H
RISC-V FCVT.WU.H Instruction Details
Instruction ManualR-typeRound half-precision FP to unsigned 32-bit integer; RV64 still sign-extends.
Instruction Syntax
fcvt.wu.h rd, rs1, rm
32-bit OP-FP fields: opcode=1010011, funct5=11000, fmt=10; rs2=00001 is a fixed selector, not a second source.
rd is x0–x31 and rs1 is f0–f31; rd=x0 discards only the integer write, while fflags still accrues.
RV32/RV64 Zfh (requires F; Zfhmin excludes this instruction); optional rm defaults to dyn using frm. Static 101/110 and dynamic frm=101–111 have reserved behavior. Enable required extensions and FP state.
Round using rm before checking 0..2^32−1: negative out-of-range/−infinity writes 0, positive out-of-range/+infinity/NaN writes 2^32−1 with NV. A changed result sets NX only without NV. RV64 sign-extends bit 31.
Sources narrower than FLEN require valid NaN-boxing, otherwise read canonical NaN. Exception flags accrue in fflags; flag setting alone causes no base FP exception trap.
ZfhFloating-Point Convert
Instruction Behavior
fcvt.wu.h rounds the half-precision value in FP register rs1 to an unsigned 32-bit integer in integer rd. Validity is checked after rounding against 0 through 2^32−1. RV64 sign-extends bit 31 to XLEN, including WU results.
FCVT.WU.H Decode And Execute Animation
Shows the Zfh-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, the rm rounding field, read the floating-point source, then write the integer destination.
rd
rs1
rm
fcvt.wu.h
,
,
Leave rm empty for the assembly default dyn (111); this DYN example fixes frm=RNE. Use lowercase rne/rtz/rdn/rup/rmm/dyn only.
Execution Context
fmt=H (10)
rs2=WU
rounding: RNE nearest-even
fflags: NX
Assume required extensions and FP state are enabled, applicable source NaN-boxing is valid, and initial fflags=0. Results preview the current input; Writeback represents commit.
31..27
26..25
24..20
19..15
14..12
11..7
6..0
11000
FCVT.WU
10
fmt=H
00001
rs2=WU
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xC4158553
opcode
1010011 -> OP-FP
funct5/fmt
11000 + 10 -> FCVT.WU.H
rs2
00001 -> WU target
rm
000 -> RNE nearest-even
rd/rs1
a0(x10) / fa1(f11)
read
fa1(f11) = 42.75
convert
42.75 -> uint32 0x0000002B (43)
write
a0(x10) = 0x0000002B (43); NX
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FCVT uses opcode 1010011.
encoding: 0xC4158553
syntax : fcvt.wu.h a0(x10), fa1(f11), rne
result : a0(x10) = 0x0000002B (43); NX
The current example rounds to a 32-bit integer according to rm and shows NX because the source has a fractional part.
FCVT Conversion View
H FP source
42.75
conversion
42.75 -> uint32 0x0000002B (43)
writeback
a0(x10) = 0x0000002B (43)
The current example rounds to a 32-bit integer according to rm and shows NX because the source has a fractional part.
This animation shows only Zfh-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.
Quick Understanding & Search Notes
fcvt.wu.h rounds the half-precision value in FP register rs1 to an unsigned 32-bit integer in integer rd. Validity is checked after rounding against 0 through 2^32−1. RV64 sign-extends bit 31 to XLEN, including WU results.
32-bit OP-FP encoding: opcode=1010011, funct5=11000, fmt=10, rs2=00001 selects WU; rs2 is not a second source register.
rd is an integer register and rs1 is an FP register; W/WU forms are available on RV32 and RV64.
rm=000/001/010/011/100 select RNE/RTZ/RDN/RUP/RMM; rm=111 uses frm. Reserved rounding modes have reserved behavior.
NX is set when the rounded result differs from the source, provided NV is not set; fflags accrues exceptions, and the base FP ISA does not trap merely because these flags are set.
Common Usage Scenarios
FP-to-unsigned-integer conversion
Understand this scenario with real code like «# f0 = 3.5; initial fflags = 0 fcvt.wu.h x10, f0, rtz # x10 = 3; NX = 1».
Pre-Use Checklist
Syntax Check
- 32-bit OP-FP fields: opcode=1010011, funct5=11000, fmt=10; rs2=00001 is a fixed selector, not a second source.
- rd is x0–x31 and rs1 is f0–f31; rd=x0 discards only the integer write, while fflags still accrues.
Semantic Check
- RV32/RV64 Zfh (requires F; Zfhmin excludes this instruction); optional rm defaults to dyn using frm. Static 101/110 and dynamic frm=101–111 have reserved behavior. Enable required extensions and FP state.
- Round using rm before checking 0..2^32−1: negative out-of-range/−infinity writes 0, positive out-of-range/+infinity/NaN writes 2^32−1 with NV. A changed result sets NX only without NV. RV64 sign-extends bit 31.
- Sources narrower than FLEN require valid NaN-boxing, otherwise read canonical NaN. Exception flags accrue in fflags; flag setting alone causes no base FP exception trap.
Pitfalls / Common Confusions
Check range after rounding: RNE converts -0.5 to 0 with NX; RDN rounds it to -1, clips to 0, and sets NV.
A rounded value below 0 or −∞ writes 0; a rounded value above 2^32−1, +∞, or NaN writes 2^32−1 with NV. NX is not set when NV is set.
RV64 sign-extends the 32-bit result; rd=x0 discards the integer write but fflags still accrues.
When the source format is narrower than FLEN, invalid NaN-boxing is read as a canonical NaN of that format.
FAQ
Does WU zero-extend on RV64?
No. The 32-bit result is sign-extended to XLEN. For example, unsigned target 2^32−1 writes 0xFFFFFFFFFFFFFFFF.