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FCVT.WU.Q

RISC-V FCVT.WU.Q Instruction Details

Instruction ManualR-type

Convert quad-precision FP to unsigned 32-bit int. In OP-FP, fmt=Q (11) and rs2=WU (00001).

Instruction Syntax

fcvt.wu.q rd, rs1, rm

Operand Breakdown

Destination rd: register receiving the operation result.

Source rs1: register holding the first operand.

Source rs2: register holding the second operand.

QFloating-Point Convert

Related Search Terms

fcvt.wu.q instruction quad-precision to unsigned 32-bit integer fcvt.wu.q conversion fcvt.wu.q rounding fcvt.wu.q floating point

Instruction Behavior

fcvt.wu.q converts a quad-precision source operand to an unsigned 32-bit integer result. Floating-point-to-integer conversion rounds according to rm and writes integer register rd.

FCVT.WU.Q Decode And Execute Animation

Shows the Q-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, the rm rounding field, read the floating-point source, then write the integer destination.

rs1

fcvt.wu.q

Execution Context

fmt=Q (11)

rs2=WU

rounding: RNE nearest-even

fflags: NX

XLEN

fa1(f11) source valueUse a finite exact example from the animation whitelistEnter a finite exact example: 0, 1, -1, 1.25, -1.5, 2, 3.5, 9; special-value paths are covered in static text

The source value is invalid and is not used for execution. The animation is using a legal FCVT.WU.Q default example value.

31..27

26..25

24..20

19..15

14..12

11..7

6..0

11000

FCVT.WU

fmt=Q

00001

rs2=WU

01011

rs1

000

01010

1010011

OP-FP

Execution Data Path

instruction

0xC6158553

opcode

1010011 -> OP-FP

funct5/fmt

11000 + 11 -> FCVT.WU.Q

rs2

00001 -> WU target

000 -> RNE nearest-even

rd/rs1

a0(x10) / fa1(f11)

read

fa1(f11) = 42.75

convert

42.75 -> uint32 0x0000002B (43)

write

a0(x10) = 0x0000002B (43); NX

Current Step

Fetch: show the 32-bit OP-FP encoding

The word is split as an R-type OP-FP instruction; FCVT uses opcode 1010011.

encoding: 0xC6158553

syntax : fcvt.wu.q a0(x10), fa1(f11), rne

result : a0(x10) = 0x0000002B (43); NX

The current example rounds to a 32-bit integer according to rm and shows NX because the source has a fractional part.

FCVT Conversion View

Q FP source

42.75

conversion

42.75 -> uint32 0x0000002B (43)

writeback

a0(x10) = 0x0000002B (43)

The current example rounds to a 32-bit integer according to rm and shows NX because the source has a fractional part.

This animation shows only Q-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.

Quick Understanding & Search Notes

fcvt.wu.q converts a quad-precision source operand to an unsigned 32-bit integer result. Floating-point-to-integer conversion rounds according to rm and writes integer register rd.

The rs2/fmt encoding selects source and destination formats; the mnemonic suffixes carry the main semantic distinction.

W/WU 32-bit integer results are extended to XLEN on RV64 according to the official rules.

Out-of-range integer targets or NaN inputs follow the official invalid floating-point-to-integer conversion rules and set NV.

The Q source occupies the FLEN=128 floating-point register width; it is not a NaN-boxed narrower-format source.

RISC-V Unprivileged ISA Manual, Q quad-precision floating-point extension

Common Usage Scenarios

Floating Point Basic

Understand this scenario with real code like «fcvt.wu.q x10, f0, rtz # x10 = (unsigned)f0».

Numerical Computing

Understand this scenario with real code like «fcvt.wu.q x10, f0, rtz # x10 = (unsigned)f0».

Pre-Use Checklist

Syntax Check

Verify rd, rs1, rs2 (and rs3) are valid GPRs.
Confirm funct3 and funct7 encoding is correct.

Semantic Check

Check if the result affects subsequent branches or address calculations.
Ensure the rd register is not overwritten by another instruction.

Pitfalls / Common Confusions