How is fcvtmod.w.d different from fcvt.w.d?
fcvtmod.w.d takes the low 32 bits of the unbounded RTZ conversion result modulo 2^32; fcvt.w.d uses the official invalid-conversion result for out-of-range integer conversion.
FCVTMOD.W.D
RISC-V FCVTMOD.W.D Instruction Details
Instruction ManualR-typeModular convert double-precision float to signed word (mod 2^32)
Instruction Syntax
fcvtmod.w.d rd, rs1, rtz
32-bit OP-FP fields: opcode=1010011, funct5=11000, fmt=01; rs2=01000 is a fixed selector, not a second source.
rd is x0–x31 and rs1 is f0–f31; rd=x0 discards only the integer write, while fflags still accrues.
RV32/RV64 Zfa+D; explicit rtz is required, rm=001, and other rm encodings are reserved. Enable required extensions and FP state.
After fixed RTZ, sign-extend the low 32 bits of the unbounded result to XLEN; NaN/infinity writes 0. Flags match FCVT.W.D with RTZ for the same input.
Sources narrower than FLEN require valid NaN-boxing, otherwise read canonical NaN. Exception flags accrue in fflags; flag setting alone causes no base FP exception trap.
ZfaDFloating-Point Convert
Instruction Behavior
fcvtmod.w.d is a Zfa instruction. It converts a double-precision value toward zero to an unbounded two's-complement integer, takes the low 32 bits, sign-extends to XLEN, and converts NaN and infinities to zero.
FCVTMOD.W.D Decode And Execute Animation
Shows the Zfa + D-extension FCVTMOD flow: decode OP-FP fields, fmt/rs2 conversion selection, fixed rm=001 (RTZ), read the floating-point source, then write the integer destination.
rd
rs1
rm
fcvtmod.w.d
,
,
Execution Context
fmt=D (01)
rs2=8 (modular W)
rounding: fixed RTZ (001)
fflags: NX
Assume required extensions and FP state are enabled, applicable source NaN-boxing is valid, and initial fflags=0. Results preview the current input; Writeback represents commit.
31..27
26..25
24..20
19..15
14..12
11..7
6..0
11000
FCVTMOD
01
fmt=D
01000
rs2=8 (modular W)
01011
rs1
001
rm=001 RTZ
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xC2859553
opcode
1010011 -> OP-FP
funct5/fmt
11000 + 01 -> FCVTMOD.W.D
rs2
01000 -> 8 (modular W) target
rm
001 -> fixed RTZ; other rm encodings are reserved
rd/rs1
a0(x10) / fa1(f11)
read
fa1(f11) = -42.75
convert
-42.75 -> int32 -42
write
a0(x10) = 0xFFFFFFD6 (-42); NX
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FCVTMOD uses opcode 1010011.
encoding: 0xC2859553
syntax : fcvtmod.w.d a0(x10), fa1(f11), rtz
result : a0(x10) = 0xFFFFFFD6 (-42); NX
The current example uses fixed RTZ, takes the low 32 bits of the unbounded two's-complement result, and sign-extends them; fflags shows the NX outcome of FCVT.W.D for the same input.
FCVTMOD Conversion View
D FP source
-42.75
conversion
-42.75 -> int32 -42
writeback
a0(x10) = 0xFFFFFFD6 (-42)
The current example uses fixed RTZ, takes the low 32 bits of the unbounded two's-complement result, and sign-extends them; fflags shows the NX outcome of FCVT.W.D for the same input.
This animation shows only Zfa + D-extension FCVTMOD ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.
Quick Understanding & Search Notes
fcvtmod.w.d is a Zfa instruction. It converts a double-precision value toward zero to an unbounded two's-complement integer, takes the low 32 bits, sign-extends to XLEN, and converts NaN and infinities to zero.
32-bit OP-FP encoding: opcode=1010011, funct5=11000, fmt=01, rs2=01000, rm=001; rs1 is the FP source and rd the integer destination.
Assembly syntax must explicitly write rtz; other rm encodings are reserved.
It is a modulo 2^32 conversion, not the saturating/clipping conversion of FCVT.W.D.
NaN and positive or negative infinity produce zero, a special rule for this Zfa instruction.
fflags is the same as FCVT.W.D for the same input; an invalid conversion sets NV.
Requires Zfa and D; available on RV32 and RV64. rd=x0 discards the integer write but does not suppress fflags.
Common Usage Scenarios
JavaScript integer conversion
Understand this scenario with real code like «# f0 = 4294967297; initial fflags = 0 fcvtmod.w.d x10, f0, rtz # x10 = 1; NV = 1».
Modulo 2^32 conversion
Understand this scenario with real code like «# f0 = 4294967297; initial fflags = 0 fcvtmod.w.d x10, f0, rtz # x10 = 1; NV = 1».
Pre-Use Checklist
Syntax Check
- 32-bit OP-FP fields: opcode=1010011, funct5=11000, fmt=01; rs2=01000 is a fixed selector, not a second source.
- rd is x0–x31 and rs1 is f0–f31; rd=x0 discards only the integer write, while fflags still accrues.
Semantic Check
- RV32/RV64 Zfa+D; explicit rtz is required, rm=001, and other rm encodings are reserved. Enable required extensions and FP state.
- After fixed RTZ, sign-extend the low 32 bits of the unbounded result to XLEN; NaN/infinity writes 0. Flags match FCVT.W.D with RTZ for the same input.
- Sources narrower than FLEN require valid NaN-boxing, otherwise read canonical NaN. Exception flags accrue in fflags; flag setting alone causes no base FP exception trap.
Pitfalls / Common Confusions
Assembly syntax must explicitly write rtz; other rm encodings are reserved.
It is a modulo 2^32 conversion, not the saturating/clipping conversion of FCVT.W.D.
NaN and positive or negative infinity produce zero, a special rule for this Zfa instruction.
FAQ
Why does fcvtmod.w.d require rtz?
Zfa requires assembly syntax to explicitly specify RTZ; other rm encodings are reserved.