Does it raise integer exceptions?
No. Floating-point exceptions are recorded in fflags and results follow the floating-point rules.
FDIV.D
RISC-V FDIV.D Instruction Details
Instruction ManualR-typeDouble-precision floating-point division: rd = rs1/rs2.
Instruction Syntax
fdiv.d rd, rs1, rs2, rm
Operand Breakdown
rd: destination floating-point register receiving the formatted result.
rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.
DFloating-Point Arithmetic
Instruction Behavior
FDIV.D divides double-precision floating-point rs1 by rs2, rounds according to rm, and writes rd. Exception flags and special-value results follow the RISC-V D extension/IEEE 754 rules.
Quick Understanding & Search Notes
FDIV.D is a floating-point arithmetic instruction. It uses the rm field for rounding mode and sets fflags exception flags according to IEEE 754/RISC-V floating-point rules.
The .D suffix uses 64-bit double precision from the D extension.
Divide-by-zero, 0/0, infinities, and NaNs are handled by floating-point result classification and exception flags.
Common Usage Scenarios
Multiplication & Division
Understand this scenario with real code like «fdiv.d f0, f1, f2 # f0 = f1/f2 (RNE)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Rounding is selected by rm or the dynamic rounding mode.
Floating-point exceptions are recorded in fflags, not integer condition flags.
Execution latency is implementation-dependent and is not ISA semantics.
FAQ
Can rm be omitted?
Assemblers may provide a dynamic/default spelling, but the machine instruction contains a rounding-mode field.