Why does FSQRT.D have no rs2 operand?
Square root is a unary FP operation. The machine encoding still has an rs2 field, but it is fixed to 00000 and does not correspond to a second source register in assembly syntax.
FSQRT.D
RISC-V FSQRT.D Instruction Details
Instruction ManualR-typeComputes double-precision floating-point square root: f[rd] = sqrt(f[rs1]).
Instruction Syntax
fsqrt.d rd, rs1, rm
Operand Breakdown
RV32/RV64 D 2.2 (dependent on F); 32-bit OP-FP, funct5=01011, fmt=01 (D) and opcode=1010011.
rd and rs1 select FP f0–f31; f0 is writable and rs2 is fixed 00000. Optional rm defaults to dyn; explicit rounding mnemonics must be lowercase.
Take the square root of rs1, round by rm/frm and write rd; rd may overlap rs1. Wider FLEN requires NaN-boxed inputs, treating failed checks as canonical NaN, and ones in upper result bits.
rm=101/110 and dynamic frm=101/110/111 have reserved behavior. Applicable NV and NX accrue in fflags; setting a flag does not itself trap. The animation covers finite exact inputs only.
DFloating-Point Arithmetic
Instruction Behavior
FSQRT.D uses OP-FP encoding with fmt=D to compute the square root of one double-precision floating-point operand, rounds according to rm or dynamic frm, and writes FP register rd. The encoded rs2 field is fixed to 00000; NaN-boxing, negative nonzero inputs, NaNs, infinities, and inexact results produce results and fflags according to the RISC-V D/F-extension FP rules.
FSQRT.D Decode And Execute Animation
Shows the D-extension double-precision OP-FP flow: decode fields, read FP operands, perform FSQRT semantics, then write rd.
rd
rs1
rm
fsqrt.d
,
,
Execution Context
FLEN=>=64 / fmt=D (01)
rounding: RNE nearest-even
fflags: initial 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
01011
FSQRT
01
fmt=D
00000
rs2
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x5A058553
opcode
1010011 -> OP-FP
funct5/fmt
01011 + D(01) -> FSQRT.D
rm
000 -> RNE nearest-even
rd/rs
fa0(f10) / fa1(f11) / rs2=00000
read
Source registers not read yet
FP op
Awaiting Execute
write
Not written yet; initial fflags=0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; double-precision OP-FP instructions use opcode 1010011.
encoding: 0x5A058553
syntax : fsqrt.d fa0(f10), fa1(f11), rne
result : Not written yet; initial fflags=0
The default example sqrt(9.0)=3.0 is exactly representable, so example fflags remains 0.
Double-precision Calculation
rs1
fa1(f11) = 9.0
result
Awaiting Execute
The default example sqrt(9.0)=3.0 is exactly representable, so example fflags remains 0.
Assumes the extension and FS are enabled, correctly NaN-boxed input, and initial fflags=0. Only 1, 2.25, and 9 are accepted, producing exact 1, 1.5, and 3 under every legal rounding mode with no flags set. Other inputs stop execution. rd may overlap the source and f0 accepts writes. Steps are teaching views.
This animation shows only D-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
Quick Understanding & Search Notes
FSQRT.D is the D-extension double-precision square root. It has one source FP register; the encoding still contains rs2 but fixes it to 00000. rm/frm controls rounding, while NaN-boxing and fflags follow the official D/F FP rules.
The syntax operands are rd, rs1, and rm; the animation does not expose rs2 as user input.
fmt=D denotes 64-bit double precision, and funct5=FSQRT selects square root.
The animation uses the exact example sqrt(9.0)=3.0, so example fflags remains 0; negative nonzero inputs, failed NaN-boxing checks, and inexact results still follow the official FP rules.
Common Usage Scenarios
Numerical Computing
Understand this scenario with real code like «fsqrt.d f0, f1, rne # f0 = sqrt(f1)».
Pre-Use Checklist
Syntax Check
- RV32/RV64 D 2.2 (dependent on F); 32-bit OP-FP, funct5=01011, fmt=01 (D) and opcode=1010011.
- rd and rs1 select FP f0–f31; f0 is writable and rs2 is fixed 00000. Optional rm defaults to dyn; explicit rounding mnemonics must be lowercase.
Semantic Check
- Take the square root of rs1, round by rm/frm and write rd; rd may overlap rs1. Wider FLEN requires NaN-boxed inputs, treating failed checks as canonical NaN, and ones in upper result bits.
- rm=101/110 and dynamic frm=101/110/111 have reserved behavior. Applicable NV and NX accrue in fflags; setting a flag does not itself trap. The animation covers finite exact inputs only.
Pitfalls / Common Confusions
FSQRT.D assembly syntax has only rd, rs1, and rm; rs2 is a fixed encoding field, not a second source operand.
D-extension double-precision operands in wider FLEN are constrained by NaN-boxing rules.
sqrt(9.0)=3.0 is the exact animation example; inexact results such as sqrt(2.0) may set NX.
The assembly rm operand is optional; omitting it selects dyn (frm), while explicit rne selects round-to-nearest, ties-to-even.
FAQ
How are negative inputs handled?
Negative nonzero inputs follow floating-point invalid-operation rules, producing the specified result and fflags; this is not an integer exception or branch condition.