Why does FSQRT.H have no rs2 operand?
FSQRT is a unary FP operation. The machine encoding still has an rs2 field, but it is fixed to 00000; the page animation shows it as an encoded field rather than a syntax input.
FSQRT.H
RISC-V FSQRT.H Instruction Details
Instruction ManualR-typeHalf-precision floating-point square root: rd = sqrt(rs1).
Instruction Syntax
fsqrt.h rd, rs1[, rm]
Operand Breakdown
rd and rs1 select FP f0–f31 or ABI names; f0 is writable and rd may overlap a source. rs2 is fixed 00000, not a source operand.
32-bit OP-FP: funct5=01011, fmt=10 (H), opcode=1010011. Optional rm defaults to dyn; explicit rm mnemonics must be lowercase.
Requires enabled FP state and Zfh 1.0 (dependent on F). H inputs are checked for NaN-boxing; failed checks are treated as canonical NaN, and upper result bits are all ones. Round sqrt(rs1) by rm/frm and write rd.
rm=101/110 and dynamic frm=101–111 have reserved behavior. Applicable NV and NX accrue in fflags; setting a flag does not itself trap. The animation covers finite exact inputs only.
ZfhFloating-Point Arithmetic
Instruction Behavior
FSQRT.H computes the half-precision floating-point square root, rounds according to rm or the dynamic rounding mode, writes rd, and accrues applicable floating-point exception conditions in fflags.
FSQRT.H Decode And Execute Animation
Shows the Zfh-extension half-precision OP-FP flow: decode fields, read FP operands, perform FSQRT semantics, then write rd.
rd
rs1
rm
fsqrt.h
,
,
Leave rm empty to use the assembly default dyn encoding and fcsr.frm below.
Execution Context
FLEN>=32 / fmt=H (10)
rounding: RNE nearest-even
fflags: initial 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
01011
FSQRT
10
fmt=H
00000
rs2
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x5C058553
opcode
1010011 -> OP-FP
funct5/fmt
01011 + H(10) -> FSQRT.H
rm
000 -> RNE nearest-even
rd/rs
fa0(f10) / fa1(f11) / rs2=00000
read
Source registers not read yet
FP op
Awaiting Execute
write
Not written yet; initial fflags=0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; half-precision OP-FP instructions use opcode 1010011.
encoding: 0x5C058553
syntax : fsqrt.h fa0(f10), fa1(f11), rne
result : Not written yet; initial fflags=0
The default example sqrt(2.25)=1.5 is exactly representable, so example fflags remains 0.
Half-precision Calculation
rs1
fa1(f11) = 2.25
result
Awaiting Execute
The default example sqrt(2.25)=1.5 is exactly representable, so example fflags remains 0.
Assumes the extension and FS are enabled, correctly NaN-boxed input, and initial fflags=0. Only 1, 2.25, and 9 are accepted, producing exact 1, 1.5, and 3 under every legal rounding mode with no flags set. Other inputs stop execution. rd may overlap the source and f0 accepts writes. Steps are teaching views.
This animation shows only Zfh-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
Quick Understanding & Search Notes
FSQRT.H is Zfh half-precision floating-point square root. It uses OP-FP encoding with funct5=01011, fmt=H(10), and rs2 fixed to 00000; it reads only the rs1 half-precision value, rounds according to rm or dynamic frm, and writes rd.
FSQRT.H has rs2 as a fixed encoded field, not an assembly operand; the syntax contains only rd, rs1, and rm.
FSQRT.H's applicable exception flags are NV and NX, accrued in fflags.
The animation accepts only exact inputs 1, 2.25, and 9, producing 1, 1.5, and 3. With initial fflags=0, no flags are added under any legal rounding mode. Other values are not executed.
Requires Zfh 1.0 (dependent on F) and enabled FP state. H inputs in wider FLEN must be correctly NaN-boxed; failed checks are treated as canonical NaN, and upper bits of H results are all ones.
Common Usage Scenarios
Floating Point Basic
Understand this scenario with real code like «fsqrt.h f0, f1, rne # f0 = sqrt(f1)».
Numerical Computing
Understand this scenario with real code like «fsqrt.h f0, f1, rne # f0 = sqrt(f1)».
Pre-Use Checklist
Syntax Check
- rd and rs1 select FP f0–f31 or ABI names; f0 is writable and rd may overlap a source. rs2 is fixed 00000, not a source operand.
- 32-bit OP-FP: funct5=01011, fmt=10 (H), opcode=1010011. Optional rm defaults to dyn; explicit rm mnemonics must be lowercase.
Semantic Check
- Requires enabled FP state and Zfh 1.0 (dependent on F). H inputs are checked for NaN-boxing; failed checks are treated as canonical NaN, and upper result bits are all ones. Round sqrt(rs1) by rm/frm and write rd.
- rm=101/110 and dynamic frm=101–111 have reserved behavior. Applicable NV and NX accrue in fflags; setting a flag does not itself trap. The animation covers finite exact inputs only.
Pitfalls / Common Confusions
Optional lowercase rm defaults to dyn; rm=111 uses frm. Static 101/110 and dynamic frm=101–111 have reserved behavior.
Floating-point exceptions accrue in fflags; setting these flags does not itself generate a trap.
FSQRT.H's applicable exception flags are NV and NX, accrued in fflags.
FAQ
Which exception flags can FSQRT.H record?
FSQRT.H's applicable exception flags are NV and NX, accrued in fflags.