Why does FSQRT.H have no rs2 operand?
FSQRT is a unary FP operation. The machine encoding still has an rs2 field, but it is fixed to 00000; the page animation shows it as an encoded field rather than a syntax input.
FSQRT.H
RISC-V FSQRT.H Instruction Details
Instruction ManualR-typeHalf-precision floating-point square root: rd = sqrt(rs1).
Instruction Syntax
fsqrt.h rd, rs1, rm
Operand Breakdown
rd: destination floating-point register receiving the square-root result.
rs1: the only source floating-point register; the encoded rs2 field is fixed to 00000 and is not a syntax operand.
rm: rounding-mode field; rm=111 uses the dynamic frm rounding mode.
ZfhFloating-Point Arithmetic
Instruction Behavior
FSQRT.H computes the half-precision floating-point square root, rounds according to rm or the dynamic rounding mode, writes rd, and accrues applicable floating-point exception conditions in fflags.
FSQRT.H Decode And Execute Animation
Shows the Zfh-extension half-precision OP-FP flow: decode fields, read FP operands, perform FSQRT semantics, then write rd.
rd
rs1
rm
fsqrt.h
,
,
Execution Context
FLEN=>=32 / fmt=H (10)
rounding: RNE nearest-even
fflags: example fflags remains 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
01011
FSQRT
10
fmt=H
00000
rs2
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x5C058553
opcode
1010011 -> OP-FP
funct5/fmt
01011 + H(10) -> FSQRT.H
rm
000 -> RNE nearest-even
rd/rs
fa0(f10) / fa1(f11) / rs2=00000
read
2.25
FP op
sqrt(2.25) = 1.5
write
fa0(f10) = 1.5; example fflags remains 0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; half-precision OP-FP instructions use opcode 1010011.
encoding: 0x5C058553
syntax : fsqrt.h fa0(f10), fa1(f11), rne
result : fa0(f10) = 1.5; example fflags remains 0
The default example sqrt(2.25)=1.5 is exactly representable, so example fflags remains 0.
Half-precision Calculation
rs1
fa1(f11) = 2.25
result
sqrt(2.25) = 1.5
The default example sqrt(2.25)=1.5 is exactly representable, so example fflags remains 0.
This animation shows only Zfh-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
Quick Understanding & Search Notes
FSQRT.H is Zfh half-precision floating-point square root. It uses OP-FP encoding with funct5=01011, fmt=H(10), and rs2 fixed to 00000; it reads only the rs1 half-precision value, rounds according to rm or dynamic frm, and writes rd.
FSQRT.H has rs2 as a fixed encoded field, not an assembly operand; the syntax contains only rd, rs1, and rm.
FSQRT.H's applicable exception flags are NV and NX, accrued in fflags.
The animation defaults to the exact example sqrt(2.25)=1.5; final results and fflags for other special values and inexact rounding follow the applicable floating-point rules.
Common Usage Scenarios
Floating Point Basic
Understand this scenario with real code like «fsqrt.h f10, f11, rne ; f10 = sqrt(f11)».
Numerical Computing
Understand this scenario with real code like «fsqrt.h f10, f11, rne ; f10 = sqrt(f11)».
Pre-Use Checklist
Syntax Check
- rd: destination floating-point register receiving the square-root result.
- rs1: the only source floating-point register; the encoded rs2 field is fixed to 00000 and is not a syntax operand.
- rm: rounding-mode field; rm=111 uses the dynamic frm rounding mode.
Semantic Check
- Confirm the floating-point format suffix (.H/.S/.D/.Q) matches the data width.
- Decide whether software must inspect fflags for NV, DZ, OF, UF, or NX.
Pitfalls / Common Confusions
Rounding comes from the rm field; rm=111 uses the dynamic frm rounding mode.
Floating-point exceptions are recorded in fflags, not as integer branch conditions or integer traps.
FSQRT.H's applicable exception flags are NV and NX, accrued in fflags.
FAQ
Which exception flags can FSQRT.H record?
FSQRT.H's applicable exception flags are NV and NX, accrued in fflags.