RISC-V FADD.H Instruction Details

Instruction ManualR-type

Half-precision floating-point add

Instruction Syntax

fadd.h rd, rs1, rs2, rm

Operand Breakdown

rd: destination floating-point register receiving the formatted result.

rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.

ZfhFloating-Point Arithmetic

Related Search Terms

fadd.h instruction half-precision add fadd.h floating point fadd.h rounding NaN boxing

Instruction Behavior

fadd.h performs IEEE 754 addition on two half-precision source operands, rounds according to rm, and writes the half-precision result to f[rd].

Quick Understanding & Search Notes

fadd.h performs IEEE 754 addition on two half-precision source operands, rounds according to rm, and writes the half-precision result to f[rd].

The rm field selects a static rounding mode; rm=111 uses the dynamic frm rounding mode.

Results and exception flags follow RISC-V floating-point and IEEE 754 rules; do not treat NaN, infinity, or rounding boundaries like integer addition.

Zfh half-precision values in wider FLEN registers must be properly NaN-boxed.

RISC-V Unprivileged ISA Manual, Zfh half-precision floating-point extension

Common Usage Scenarios

Floating Point Basic

Understand this scenario with real code like «fadd.h f10, f11, f12, rne ; f10 = f11 + f12».

Machine Learning

Understand this scenario with real code like «fadd.h f10, f11, f12, rne ; f10 = f11 + f12».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is R-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions