What does rm do for FADD.H?
rm selects the floating-point rounding mode; rm=111 uses dynamic frm. If the result is exactly representable, rounding does not change the example value, but the encoded field still matters.
FADD.H
RISC-V FADD.H Instruction Details
Instruction ManualR-typeHalf-precision floating-point addition, OP-FP fmt=H(10).
Instruction Syntax
fadd.h rd, rs1, rs2, rm
Operand Breakdown
rd: destination floating-point register receiving the formatted result.
rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.
ZfhFloating-Point Arithmetic
Instruction Behavior
FADD.H performs half-precision floating-point addition on two FP source operands, rounds according to the rm field or dynamic frm, writes the result to FP register rd, and records fflags according to RISC-V floating-point rules.
FADD.H Decode And Execute Animation
Shows the Zfh-extension half-precision OP-FP flow: decode fields, read FP operands, perform FADD semantics, then write rd.
rd
rs1
rs2
rm
fadd.h
,
,
,
Execution Context
FLEN=>=32 / fmt=H (10)
rounding: RNE nearest-even
fflags: example fflags remains 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
00000
FADD
10
fmt=H
01100
rs2
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x04C58553
opcode
1010011 -> OP-FP
funct5/fmt
00000 + H(10) -> FADD.H
rm
000 -> RNE nearest-even
rd/rs
fa0(f10) / fa1(f11) / fa2(f12)
read
1.5, 0.5
FP op
1.5 + 0.5 = 2.0
write
fa0(f10) = 2.0; example fflags remains 0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; half-precision OP-FP instructions use opcode 1010011.
encoding: 0x04C58553
syntax : fadd.h fa0(f10), fa1(f11), fa2(f12), rne
result : fa0(f10) = 2.0; example fflags remains 0
The H/Q animation accepts only finite whitelisted examples whose inputs and result are exactly checkable; this example needs no rounding and sets no FP exception flags. NaN, infinity, overflow, underflow, and inexact paths are covered in static text.
Half-precision Calculation
rs1
fa1(f11) = 1.5
rs2
fa2(f12) = 0.5
result
1.5 + 0.5 = 2.0
The H/Q animation accepts only finite whitelisted examples whose inputs and result are exactly checkable; this example needs no rounding and sets no FP exception flags. NaN, infinity, overflow, underflow, and inexact paths are covered in static text.
This animation shows only Zfh-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
Quick Understanding & Search Notes
FADD.H is a Zfh-extension half-precision OP-FP arithmetic instruction. It decodes funct5=00000 with fmt=H(10), reads f[rs1] and f[rs2], performs addition, rounds by rm/frm, and writes f[rd].
fmt=H(10) selects the half-precision floating-point format; the opcode remains OP-FP 1010011.
The rm field selects a static rounding mode, while rm=111 uses dynamic frm; exact examples keep the same numeric value but the field is still encoded.
Applicable inexact, overflow, underflow, invalid-operation, and related cases are accrued in fflags; this is not integer arithmetic or condition-code update.
Zfh H-format values in wider FLEN floating-point registers follow NaN-boxing rules.
Common Usage Scenarios
Floating-point arithmetic
Understand this scenario with real code like «fadd.h f10, f11, f12, rne ; f10 = f11 + f12».
Pre-Use Checklist
Syntax Check
- rd: destination floating-point register receiving the formatted result.
- rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.
Semantic Check
- Confirm the floating-point format suffix (.H/.S/.D/.Q) matches the data width.
- Decide whether software must inspect fflags for NV, DZ, OF, UF, or NX.
Pitfalls / Common Confusions
Results and exception flags follow RISC-V floating-point and IEEE 754 rules; do not treat NaN, infinity, or rounding boundaries like integer addition.
Zfh half-precision values in wider FLEN registers must be properly NaN-boxed.
FAQ
Does FADD.H write integer registers or condition codes?
FADD.H writes FP register f[rd]. RISC-V floating-point exceptions are accrued in fflags, not reported through integer condition codes.