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FDIV.H

RISC-V FDIV.H Instruction Details

Instruction ManualR-type

Half-precision floating-point division: rd = rs1 / rs2.

Instruction Syntax

fdiv.h rd, rs1, rs2, rm
Operand Breakdown
rd: destination floating-point register receiving the formatted result.
rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.
ZfhFloating-Point Arithmetic
Related Search Terms
FDIV.H instructionRISC-V FDIV.Hfdiv.h syntaxfdiv.h encodingfdiv.h roundinghalf-precision FP divideRISC-V Zfh extension

Instruction Behavior

FDIV.H performs half-precision floating-point division for fdiv.h, rounds the result according to rm or the dynamic rounding mode, and writes rd. Special values, NaNs, infinities, divide-by-zero cases, and exception flags follow the IEEE 754 rules adopted by the RISC-V floating-point extensions.

FDIV.H Decode And Execute Animation

Shows the Zfh-extension half-precision OP-FP flow: decode fields, read FP operands, perform FDIV semantics, then write rd.

rd
rs1
rs2
rm
fdiv.h
,
,
,
Execution Context
FLEN=>=32 / fmt=H (10)
rounding: RNE nearest-even
fflags: example fflags remains 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
00011
FDIV
10
fmt=H
01100
rs2
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x1CC58553
opcode
1010011 -> OP-FP
funct5/fmt
00011 + H(10) -> FDIV.H
rm
000 -> RNE nearest-even
rd/rs
fa0(f10) / fa1(f11) / fa2(f12)
read
3.0, 1.5
FP op
3.0 / 1.5 = 2.0
write
fa0(f10) = 2.0; example fflags remains 0
Current Step

Fetch: show the 32-bit OP-FP encoding

The word is split as an R-type OP-FP instruction; half-precision OP-FP instructions use opcode 1010011.

encoding: 0x1CC58553
syntax : fdiv.h fa0(f10), fa1(f11), fa2(f12), rne
result : fa0(f10) = 2.0; example fflags remains 0

The default example 3.0 / 1.5 = 2.0 is exactly representable, so example fflags remains 0.

Half-precision Calculation
rs1
fa1(f11) = 3.0
rs2
fa2(f12) = 1.5
result
3.0 / 1.5 = 2.0

The default example 3.0 / 1.5 = 2.0 is exactly representable, so example fflags remains 0.

This animation shows only Zfh-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.

Quick Understanding & Search Notes

FDIV.H is Zfh half-precision floating-point division. It uses OP-FP encoding with funct5=00011 and fmt=H(10), reads two half-precision FP operands, rounds according to rm or dynamic frm, writes rd, and accrues applicable FP exception flags in fflags.

In OP-FP, opcode=1010011, funct5=00011 selects FDIV, and fmt=10 selects the H half-precision format.
rm is an encoded field; rm=111 uses the dynamic frm rounding mode. Exactly representable examples do not change with rm.
Divide-by-zero, invalid operation, overflow, underflow, and inexact results are recorded in fflags; the page animation computes only finite exactly checkable teaching examples.
RISC-V Unprivileged ISA Manual: Zfh Extension

Common Usage Scenarios

Floating Point Basic

Understand this scenario with real code like «fdiv.h f10, f11, f12, rne ; f10 = f11 / f12».

Numerical Computing

Understand this scenario with real code like «fdiv.h f10, f11, f12, rne ; f10 = f11 / f12».

Pre-Use Checklist

Syntax Check
  • rd: destination floating-point register receiving the formatted result.
  • rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.
Semantic Check
  • Confirm the floating-point format suffix (.H/.S/.D/.Q) matches the data width.
  • Decide whether software must inspect fflags for NV, DZ, OF, UF, or NX.

Pitfalls / Common Confusions

Rounding comes from the rm field; rm=111 uses the dynamic frm rounding mode.
Floating-point exceptions are recorded in fflags, not as integer branch conditions or integer traps.
0/0, nonzero divided by zero, NaNs, and infinities follow IEEE 754/RISC-V floating-point result rules.

FAQ

Why does the FDIV.H animation restrict input values?

Half-precision boundary cases, NaNs, infinities, and rounding combinations are numerous. The animation accepts only finite exactly checkable examples to avoid misleading JavaScript numeric modeling; full boundary behavior follows the official FP rules and static text.

Does FDIV.H raise an integer exception for division by zero?

No. Floating-point divide-by-zero and related cases are recorded through FP exception flags in fflags, and the result is determined by the IEEE 754 FP rules adopted by RISC-V.