Half-precision floating-point division: rd = rs1 / rs2.
32-bit OP-FP fields: opcode=1010011, funct5=00011, fmt=10; rs2 is the second FP source.
rd, rs1, rs2 are f0–f31; f0 is writable and rd may overlap a source. One source register must have one initial value.
RV32/RV64 Zfh (requires F; Zfhmin excludes this instruction); optional rm defaults to dyn using frm. Static 101/110 and dynamic frm=101–111 have reserved behavior. Enable required extensions and FP state.
Compute half-precision rs1/rs2 and round with rm. The animation accepts only nonzero finite exact whitelisted inputs and results with initial fflags=0; boundaries are outside it.
Sources narrower than FLEN require valid NaN-boxing, otherwise read canonical NaN. Exception flags accrue in fflags; flag setting alone causes no base FP exception trap.
FDIV.H performs half-precision floating-point division for fdiv.h, rounds the result according to rm or the dynamic rounding mode, and writes rd. Special values, NaNs, infinities, divide-by-zero cases, and exception flags follow the IEEE 754 rules adopted by the RISC-V floating-point extensions.
Shows the Zfh-extension half-precision OP-FP flow: decode fields, read FP operands, perform FDIV semantics, then write rd.
Leave rm empty to use the assembly default dyn encoding and fcsr.frm below.
The word is split as an R-type OP-FP instruction; half-precision OP-FP instructions use opcode 1010011.
The default example 3.0 / 1.5 = 2.0 is exactly representable, so example fflags remains 0.
The default example 3.0 / 1.5 = 2.0 is exactly representable, so example fflags remains 0.
Assumes the extension is available, FS enabled, correctly NaN-boxed inputs, and initial fflags=0. Only nonzero finite exact whitelisted inputs and nonzero whitelisted results are accepted; zero and rounding/exception boundaries are outside this animation. One source register must have one initial value; rd may overlap a source, and f0 accepts writeback. Steps are teaching views.
This animation shows only Zfh-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
FDIV.H is Zfh half-precision floating-point division. It uses OP-FP encoding with funct5=00011 and fmt=H(10), reads two half-precision FP operands, rounds according to rm or dynamic frm, writes rd, and accrues applicable FP exception flags in fflags.
Understand this scenario with real code like «# f11 = 7.5; f12 = 2.5; initial fflags = 0 fdiv.h f10, f11, f12, rne # f10 = 3; fflags = 0».
Understand this scenario with real code like «# f11 = 7.5; f12 = 2.5; initial fflags = 0 fdiv.h f10, f11, f12, rne # f10 = 3; fflags = 0».
Half-precision boundary cases, NaNs, infinities, and rounding combinations are numerous. The animation accepts only finite exactly checkable examples to avoid misleading JavaScript numeric modeling; full boundary behavior follows the official FP rules and static text.
No. Floating-point divide-by-zero and related cases are recorded through FP exception flags in fflags, and the result is determined by the IEEE 754 FP rules adopted by RISC-V.