Does FSUB.H raise integer exceptions?
No. RISC-V floating-point exceptions are accrued in fflags; software reads floating-point status state to observe them.
Half-precision floating-point subtraction: rd = rs1 - rs2.
FSUB.H performs half-precision floating-point subtraction for fsub.h, rounds the result according to rm or the dynamic rounding mode, and writes rd. Special values, NaNs, infinities, divide-by-zero cases, and exception flags follow the IEEE 754 rules adopted by the RISC-V floating-point extensions.
FSUB.H is a Zfh-related half-precision floating-point subtraction instruction. It produces a floating-register result, uses rm when rounding is required, and records floating-point exception flags such as NV, DZ, OF, UF, and NX in fflags.
Understand this scenario with real code like «fsub.h f10, f11, f12, rne ; f10 = f11 - f12».
Understand this scenario with real code like «fsub.h f10, f11, f12, rne ; f10 = f11 - f12».
No. RISC-V floating-point exceptions are accrued in fflags; software reads floating-point status state to observe them.
rm selects the rounding mode; the dynamic rounding mode comes from frm. For exact results it does not change the value, but the field is still part of the instruction encoding.