What does rm do for FSUB.H?
rm selects the floating-point rounding mode; rm=111 uses dynamic frm. If the result is exactly representable, rounding does not change the example value, but the encoded field still matters.
FSUB.H
RISC-V FSUB.H Instruction Details
Instruction ManualR-typeHalf-precision floating-point subtraction, OP-FP fmt=H(10).
Instruction Syntax
fsub.h rd, rs1, rs2[, rm]
Operand Breakdown
rd, rs1 and rs2 select FP f0–f31 or ABI names; f0 is writable and rd may overlap a source. Equal source registers require one initial value.
32-bit OP-FP: funct5=00001, fmt=10 (H), opcode=1010011. Optional rm defaults to dyn; explicit rm mnemonics must be lowercase.
Requires enabled FP state and Zfh 1.0 (dependent on F). H inputs are checked for NaN-boxing; failed checks are treated as canonical NaN, and upper result bits are all ones. Round rs1-rs2 by rm/frm and write rd.
rm=101/110 and dynamic frm=101–111 have reserved behavior. Applicable NV, OF and NX accrue in fflags; setting a flag does not itself trap. The animation covers finite exact inputs only.
ZfhFloating-Point Arithmetic
Instruction Behavior
FSUB.H performs half-precision floating-point subtraction on two FP source operands, rounds according to the rm field or dynamic frm, writes the result to FP register rd, and records fflags according to RISC-V floating-point rules.
FSUB.H Decode And Execute Animation
Shows the Zfh-extension half-precision OP-FP flow: decode fields, read FP operands, perform FSUB semantics, then write rd.
rd
rs1
rs2
rm
fsub.h
,
,
,
Leave rm empty to use the assembly default dyn encoding and fcsr.frm below.
Execution Context
FLEN>=32 / fmt=H (10)
rounding: RNE nearest-even
fflags: initial 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
00001
FSUB
10
fmt=H
01100
rs2
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x0CC58553
opcode
1010011 -> OP-FP
funct5/fmt
00001 + H(10) -> FSUB.H
rm
000 -> RNE nearest-even
rd/rs
fa0(f10) / fa1(f11) / fa2(f12)
read
Source registers not read yet
FP op
Awaiting Execute
write
Not written yet; initial fflags=0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; half-precision OP-FP instructions use opcode 1010011.
encoding: 0x0CC58553
syntax : fsub.h fa0(f10), fa1(f11), fa2(f12), rne
result : Not written yet; initial fflags=0
The whitelisted inputs and nonzero result are exactly representable. With initial fflags=0, no flags are added under any legal rounding mode. Zero, special values, and rounding boundaries are outside this animation.
Half-precision Calculation
rs1
fa1(f11) = 3.5
rs2
fa2(f12) = 1.25
result
Awaiting Execute
The whitelisted inputs and nonzero result are exactly representable. With initial fflags=0, no flags are added under any legal rounding mode. Zero, special values, and rounding boundaries are outside this animation.
Assumes the extension is available, FS enabled, correctly NaN-boxed inputs, and initial fflags=0. Only nonzero finite exact whitelisted inputs and nonzero whitelisted results are accepted; zero and rounding/exception boundaries are outside this animation. One source register must have one initial value; rd may overlap a source, and f0 accepts writeback. Steps are teaching views.
This animation shows only Zfh-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
Quick Understanding & Search Notes
FSUB.H is a Zfh-extension half-precision OP-FP arithmetic instruction. It decodes funct5=00001 with fmt=H(10), reads f[rs1] and f[rs2], performs subtraction, rounds by rm/frm, and writes f[rd].
fmt=H(10) selects the half-precision floating-point format; the opcode remains OP-FP 1010011.
The rm field selects a static rounding mode, while rm=111 uses dynamic frm; exact examples keep the same numeric value but the field is still encoded.
FSUB's applicable FP exception flags are NV, OF, and NX, accrued in fflags; this is not integer arithmetic or condition-code update.
Zfh H-format values in wider FLEN floating-point registers follow NaN-boxing rules.
Requires Zfh 1.0 (dependent on F) and enabled FP state. H inputs in wider FLEN must be correctly NaN-boxed; failed checks are treated as canonical NaN, and upper bits of H results are all ones.
The animation accepts nonzero finite exact whitelisted inputs and a nonzero whitelisted result. Equal source registers must have one initial value; rd may overlap a source and f0 is writable. Zero, special values, and rounding boundaries are outside the animation.
Common Usage Scenarios
Floating-point arithmetic
Understand this scenario with real code like «fsub.h f0, f1, f2, rne # f0 = f1 - f2».
Pre-Use Checklist
Syntax Check
- rd, rs1 and rs2 select FP f0–f31 or ABI names; f0 is writable and rd may overlap a source. Equal source registers require one initial value.
- 32-bit OP-FP: funct5=00001, fmt=10 (H), opcode=1010011. Optional rm defaults to dyn; explicit rm mnemonics must be lowercase.
Semantic Check
- Requires enabled FP state and Zfh 1.0 (dependent on F). H inputs are checked for NaN-boxing; failed checks are treated as canonical NaN, and upper result bits are all ones. Round rs1-rs2 by rm/frm and write rd.
- rm=101/110 and dynamic frm=101–111 have reserved behavior. Applicable NV, OF and NX accrue in fflags; setting a flag does not itself trap. The animation covers finite exact inputs only.
Pitfalls / Common Confusions
Optional lowercase rm defaults to dyn; rm=111 uses frm. Static 101/110 and dynamic frm=101–111 have reserved behavior.
Floating-point exceptions accrue in fflags; setting these flags does not itself generate a trap.
Invalid-operation, overflow, and inexact results are reported through floating-point exception flags; the listed FSUB flags do not include UF.
FAQ
Does FSUB.H write integer registers or condition codes?
FSUB.H writes FP register f[rd]. RISC-V floating-point exceptions are accrued in fflags, not reported through integer condition codes.