What does rm do for FMUL.H?
rm selects the floating-point rounding mode; rm=111 uses dynamic frm. If the result is exactly representable, rounding does not change the example value, but the encoded field still matters.
FMUL.H
RISC-V FMUL.H Instruction Details
Instruction ManualR-typeHalf-precision floating-point multiplication, OP-FP fmt=H(10).
Instruction Syntax
fmul.h rd, rs1, rs2, rm
Operand Breakdown
rd, rs1, rs2: FP registers f0–f31 or their ABI names; f0 is writable, rd may overlap a source, and overlapping sources read one initial value.
Optional lowercase rm defaults to dyn; rm=111 uses frm. Static 101/110 and dynamic frm=101–111 have reserved behavior.
ZfhFloating-Point Arithmetic
Instruction Behavior
FMUL.H performs half-precision floating-point multiplication on two FP source operands, rounds according to the rm field or dynamic frm, writes the result to FP register rd, and records fflags according to RISC-V floating-point rules.
FMUL.H Decode And Execute Animation
Shows the Zfh-extension half-precision OP-FP flow: decode fields, read FP operands, perform FMUL semantics, then write rd.
rd
rs1
rs2
rm
fmul.h
,
,
,
Leave rm empty to use the assembly default dyn encoding and fcsr.frm below.
Execution Context
FLEN>=32 / fmt=H (10)
rounding: RNE nearest-even
fflags: initial 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
00010
FMUL
10
fmt=H
01100
rs2
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x14C58553
opcode
1010011 -> OP-FP
funct5/fmt
00010 + H(10) -> FMUL.H
rm
000 -> RNE nearest-even
rd/rs
fa0(f10) / fa1(f11) / fa2(f12)
read
Source registers not read yet
FP op
Awaiting Execute
write
Not written yet; initial fflags=0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; half-precision OP-FP instructions use opcode 1010011.
encoding: 0x14C58553
syntax : fmul.h fa0(f10), fa1(f11), fa2(f12), rne
result : Not written yet; initial fflags=0
This animation accepts only finite whitelisted examples whose inputs and result are exactly checkable; this example needs no rounding and sets no FP exception flags. NaN, infinity, overflow, underflow, and inexact paths are covered in static text.
Half-precision Calculation
rs1
fa1(f11) = 1.5
rs2
fa2(f12) = 2.0
result
Awaiting Execute
This animation accepts only finite whitelisted examples whose inputs and result are exactly checkable; this example needs no rounding and sets no FP exception flags. NaN, infinity, overflow, underflow, and inexact paths are covered in static text.
Assumes the extension is available, FS enabled, correctly NaN-boxed inputs, and initial fflags=0. Only nonzero finite exact whitelisted inputs and nonzero whitelisted results are accepted; zero and rounding/exception boundaries are outside this animation. One source register must have one initial value; rd may overlap a source, and f0 accepts writeback. Steps are teaching views.
This animation shows only Zfh-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
Quick Understanding & Search Notes
FMUL.H is a Zfh-extension half-precision OP-FP arithmetic instruction. It decodes funct5=00010 with fmt=H(10), reads f[rs1] and f[rs2], performs multiplication, rounds by rm/frm, and writes f[rd].
fmt=H(10) selects the half-precision floating-point format; the opcode remains OP-FP 1010011.
The rm field selects a static rounding mode; rm=101 and 110 are reserved, rm=111 uses dynamic frm, and frm=101 through 111 also gives reserved behavior.
Applicable NV, OF, UF, and NX accrue in fflags; an exact finite product adds none of these flags and does not clear existing flags.
Full Zfh depends on F; Zfhmin excludes H-format arithmetic; FLEN≥32. Available on RV32/RV64 with the required extensions and enabled FP state.
rd and all sources are FP registers f0–f31; f0 is writable. Overlapping sources read one initial value before writeback, and rd may overlap a source.
When the source format is narrower than FLEN, all upper bits must be 1 for valid NaN-boxing. Invalid boxes are read as canonical NaNs of that format; narrower result writes set every upper bit to 1.
The optional assembly rm operand must be lowercase and defaults to dyn. The animation starts with fflags=0 and accepts only nonzero finite exact whitelisted inputs and results. Special values, zero results, and rounding boundaries are not executed; steps are not processor cycles.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture (Version 20260120)The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture (Version 20260120)The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture (Version 20260120)The RISC-V Instruction Set Manual, Volume II: Privileged Architecture (Version 20260120)RISC-V Assembly Programmer’s Manual (Version v0.0.0, 2025-02-05; release v0.0.1)RISC-V ABIs Specification (v1.0)
Common Usage Scenarios
Floating-point arithmetic
Understand this scenario with real code like «fmul.h f0, f1, f2, rne # f1=1.5, f2=2 => f0=3».
Pre-Use Checklist
Syntax Check
- rd, rs1, rs2: FP registers f0–f31 or their ABI names; f0 is writable, rd may overlap a source, and overlapping sources read one initial value.
- Optional lowercase rm defaults to dyn; rm=111 uses frm. Static 101/110 and dynamic frm=101–111 have reserved behavior.
Semantic Check
- Confirm the source format and required extensions match and FP state is enabled; formats narrower than FLEN require valid NaN-boxing.
- Applicable NV, OF, UF, and NX accrue in fflags, without DZ; setting exception flags does not itself trap.
Pitfalls / Common Confusions
Rounding comes from the rm field; rm=101 and 110 are reserved, while rm=111 selects frm and frm=101 through 111 gives reserved behavior.
Applicable NV, OF, UF, and NX accrue in fflags. This instruction does not raise DZ; setting FP exception flags does not itself trap.
Unless otherwise specified, a NaN floating-point result is the canonical NaN of its format; fflags records the applicable exception conditions.
FAQ
Does FMUL.H write integer registers or condition codes?
FMUL.H writes FP register f[rd]. RISC-V floating-point exceptions are accrued in fflags, not reported through integer condition codes.