Performs single-precision floating-point division: f[rd] = f[rs1] / f[rs2].
FDIV.S uses OP-FP encoding with fmt=S to divide two single-precision floating-point operands, rounds according to rm or dynamic frm, and writes the result to FP register rd. Divide-by-zero, 0/0, infinities, NaNs, inexact, overflow, and underflow cases produce results and fflags according to the RISC-V F-extension floating-point rules; not every zero-divisor case is the same result.
Shows the F-extension single-precision OP-FP flow: decode fields, read FP operands, perform FDIV semantics, then write rd.
The word is split as an R-type OP-FP instruction; single-precision OP-FP instructions use opcode 1010011.
The default example 7.5 / 2.5 = 3.0 is exactly representable, so example fflags remains 0.
The default example 7.5 / 2.5 = 3.0 is exactly representable, so example fflags remains 0.
This animation shows only F-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
FDIV.S is the F-extension single-precision divide. The machine encoding uses opcode=OP-FP, funct5=FDIV, fmt=S, and rm; the result is written to an FP register, while special values and exception flags follow the official FP rules.
Understand this scenario with real code like «fdiv.s f0, f1, f2 # f0 = f1/f2 (RNE)».
The animation teaches encoding, register read, rounding-field decode, and the ordinary execution path. Zero divisors, 0/0, NaNs, and infinities are covered in static text to avoid oversimplifying special-value rules.
It does not report results through integer condition codes; floating-point exceptions are recorded in fflags and results follow the RISC-V FP rules.