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FDIV.S

RISC-V FDIV.S Instruction Details

Instruction ManualR-type

Performs single-precision floating-point division: f[rd] = f[rs1] / f[rs2].

Instruction Syntax

fdiv.s rd, rs1, rs2, rm
Operand Breakdown
RV32/RV64 F; 32-bit OP-FP, opcode=1010011, funct5=00011 and fmt=00 (S).
rd, rs1 and rs2 select FP registers f0–f31; f0 is writable. rm is optional and defaults to dyn; explicit rounding mnemonics must be lowercase.
Round rs1/rs2 according to rm/frm and write rd. One source register has one initial value; rd may overlap a source. Wider FLEN uses NaN-boxing.
rm=101/110 and dynamic frm=101/110/111 have reserved behavior. Applicable NV, DZ, OF, UF and NX flags accrue in fflags; setting a flag does not itself trap.
FFloating-Point Arithmetic
Related Search Terms
FDIV.S instructionRISC-V FDIV.Sfdiv.s syntaxfdiv.s encodingfdiv.s rmFDIV.S fflagssingle-precision float divide

Instruction Behavior

FDIV.S uses OP-FP encoding with fmt=S to divide two single-precision FP operands, rounds according to rm or dynamic frm, and writes FP register rd. The F extension is available on RV32 and RV64; FP state must be accessible. Applicable NV, DZ, OF, UF, and NX flags accrue in fflags; setting them does not itself trap. Inputs and results in wider FLEN follow NaN-boxing rules.

FDIV.S Decode And Execute Animation

Shows the F-extension single-precision OP-FP flow: decode fields, read FP operands, perform FDIV semantics, then write rd.

rd
rs1
rs2
rm
fdiv.s
,
,
,
Execution Context
FLEN=>=32 / fmt=S (00)
rounding: RNE nearest-even
fflags: initial 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
00011
FDIV
00
fmt=S
01100
rs2
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x18C58553
opcode
1010011 -> OP-FP
funct5/fmt
00011 + S(00) -> FDIV.S
rm
000 -> RNE nearest-even
rd/rs
fa0(f10) / fa1(f11) / fa2(f12)
read
Source registers not read yet
FP op
Awaiting Execute
write
Not written yet; initial fflags=0
Current Step

Fetch: show the 32-bit OP-FP encoding

The word is split as an R-type OP-FP instruction; single-precision OP-FP instructions use opcode 1010011.

encoding: 0x18C58553
syntax : fdiv.s fa0(f10), fa1(f11), fa2(f12), rne
result : Not written yet; initial fflags=0

The default example 7.5 / 2.5 = 3.0 is exactly representable, so example fflags remains 0.

Single-precision Calculation
rs1
fa1(f11) = 7.5
rs2
fa2(f12) = 2.5
result
Awaiting Execute

The default example 7.5 / 2.5 = 3.0 is exactly representable, so example fflags remains 0.

Assumes the extension is available, FS enabled, correctly NaN-boxed inputs, and initial fflags=0. Only nonzero finite exact whitelisted inputs and nonzero whitelisted results are accepted; zero and rounding/exception boundaries are outside this animation. One source register must have one initial value; rd may overlap a source, and f0 accepts writeback. Steps are teaching views.

This animation shows only F-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.

Quick Understanding & Search Notes

FDIV.S is the F-extension single-precision divide. The machine encoding uses opcode=OP-FP, funct5=FDIV, fmt=S, and rm; the result is written to an FP register, while special values and exception flags follow the official FP rules.

rd, rs1, and rs2 are FP registers; f0 accepts writeback. An explicit rm uses lowercase rne/rtz/rdn/rup/rmm/dyn; omission defaults to dyn. Source values and fflags are execution context.
fmt=S denotes 32-bit single precision; rounding comes from rm or dynamic frm.
The animation assumes available extension and FP state, valid NaN-boxing, and initial fflags=0. It accepts nonzero finite whitelisted inputs and a nonzero exact whitelisted result, such as 7.5/2.5=3.0. Invalid or conflicting input stops execution.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — F, Version 2.2The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — NaN Boxing of Narrower ValuesRISC-V Assembly Programmer’s Manual — Floating-point rounding modes

Common Usage Scenarios

Multiplication & Division

Understand this scenario with real code like «fdiv.s f0, f1, f2, rne # f1=7.5, f2=2.5 -> f0=3.0; initial fflags=0».

Pre-Use Checklist

Syntax Check
  • RV32/RV64 F; 32-bit OP-FP, opcode=1010011, funct5=00011 and fmt=00 (S).
  • rd, rs1 and rs2 select FP registers f0–f31; f0 is writable. rm is optional and defaults to dyn; explicit rounding mnemonics must be lowercase.
Semantic Check
  • Round rs1/rs2 according to rm/frm and write rd. One source register has one initial value; rd may overlap a source. Wider FLEN uses NaN-boxing.
  • rm=101/110 and dynamic frm=101/110/111 have reserved behavior. Applicable NV, DZ, OF, UF and NX flags accrue in fflags; setting a flag does not itself trap.

Pitfalls / Common Confusions

rm=111 selects dynamic frm rounding; other valid rm values are static rounding modes.
Floating-point exceptions are recorded in fflags, not integer traps or condition codes.
rm=101/110 and dynamic frm=101/110/111 are reserved rounding modes; do not assume a result.

FAQ

Why does the FDIV.S animation not directly show division by zero?

The animation is limited to nonzero finite exact examples to show encoding, source reads, rounding fields, and writeback. Zero, NaN, infinity, and inexact boundaries are outside its input range; default results do not stand in for these paths.

Does setting an FP exception flag with FDIV.S cause a trap?

No. FP arithmetic exceptions accrue in fflags; setting a flag does not itself trap. Instruction-access conditions, such as an unavailable extension or disabled FP state, are separate.