Is rd a floating-point register for FEQ.D?
No. rd is an integer register holding the Boolean result 0 or 1.
FEQ.D
RISC-V FEQ.D Instruction Details
Instruction ManualR-typeDouble-precision floating-point equality compare; writes the 0/1 Boolean result to integer register rd.
Instruction Syntax
feq.d rd, rs1, rs2
32-bit OP-FP: opcode=1010011, funct5=10100, fmt=01; funct3=010, no rm.
rd is integer x0–x31; rs1/rs2 are FP f0–f31 or ABI names. x0 discards the result while retaining NV side effects.
RV32/RV64 D (requires F); enable required extensions and FP state. Sources narrower than FLEN require valid NaN-boxing, otherwise use canonical qNaN.
Write 1 for equality, otherwise 0; any NaN writes 0. Only sNaN sets NV; qNaN does not clear old NV. fflags accrues exceptions.
One source register must have one initial value. The animation starts with fflags=0; teaching steps are not hardware cycles.
DFloating-Point Compare
Instruction Behavior
FEQ.D belongs to the D extension, which depends on F. It compares the double-precision floating-point values in f[rs1] and f[rs2], then writes the Boolean result to integer register rd. FEQ is a quiet comparison: a quiet NaN makes the result 0 without setting NV, while a signaling NaN sets NV. The comparison result is not a floating-point value and the instruction has no rm operand.
FEQ.D Decode And Execute Animation
Shows the D-extension double-precision OP-FP flow: decode fields, read FP operands, perform FEQ semantics, then write rd.
rd
rs1
rs2
feq.d
,
,
Execution Context
FLEN>=64 / fmt=D (01)
funct3: equality compare
fflags: initial 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
10100
FEQ
01
fmt=D
01100
rs2
01011
rs1
010
funct3=010
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xA2C5A553
opcode
1010011 -> OP-FP
funct5/fmt
10100 + D(01) -> FEQ.D
funct3
010 -> equality compare
rd/rs
a0(x10) / fa1(f11) / fa2(f12)
read
Source registers not read yet
FP op
Awaiting Execute
write
Not written yet; initial fflags=0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; double-precision OP-FP instructions use opcode 1010011.
encoding: 0xA2C5A553
syntax : feq.d a0(x10), fa1(f11), fa2(f12)
result : Not written yet; initial fflags=0
The comparison result is written to integer register x[rd] and is only 0 or 1; compare instructions do not use rm.
Double-precision Calculation
rs1
fa1(f11) = 1.5
rs2
fa2(f12) = 1.5
result
Awaiting Execute
The comparison result is written to integer register x[rd] and is only 0 or 1; compare instructions do not use rm.
Assumes required extensions and FS enabled, valid NaN-boxing, and initial fflags=0. Finite inputs use the exact whitelist; signed zeros, infinities, qNaN, and sNaN are supported. Other inputs stop execution. One source register must have one initial value; rd=x0 discards only the integer write while NV still accrues. Steps are teaching views.
This animation shows only D-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
Quick Understanding & Search Notes
In the D extension, which depends on F, FEQ.D bridges FP comparison to an integer Boolean result: it reads two FP registers but writes x[rd]=0/1.
funct5=10100 and funct3=010 select FEQ, while fmt=01 selects the D format.
Any NaN produces result 0; quiet NaN does not set NV, while signaling NaN sets NV.
rd is an integer register; the instruction has no rm rounding field.
NV accrues: qNaN does not set NV or clear an existing NV flag. rd=x0 discards only the integer result; flag side effects remain.
When the source format is narrower than FLEN, an incorrectly NaN-boxed source is treated as canonical qNaN. The animation assumes valid NaN-boxing, required extensions and FP state enabled, and initial fflags=0.
Common Usage Scenarios
Comparison & Detection
Understand this scenario with real code like «feq.d x10, f0, f1 # f0=1.5, f1=1.5 -> x10=1; no new flags».
Floating-Point Conditions
Understand this scenario with real code like «feq.d x10, f0, f1 # f0=1.5, f1=1.5 -> x10=1; no new flags».
Pre-Use Checklist
Syntax Check
- rd: destination integer register receiving a 0 or 1 comparison result.
- rs1/rs2: source floating-point registers; compare instructions do not use an rm rounding mode.
Semantic Check
- Confirm the result is written to an integer register and is only 0 or 1.
- Confirm quiet/signaling comparison behavior for NaNs and NV matches the need.
Pitfalls / Common Confusions
FEQ sets NV only for signaling NaNs; a quiet NaN produces result 0.
rd is an integer register and receives 0 or 1, not a floating-point register.
The comparison has no rm field and performs no floating-point rounding.
FAQ
How does FEQ.D handle NaN operands?
Any NaN produces result 0; FEQ sets NV only for signaling NaN.
Does FEQ.D use rm rounding?
No. FP comparisons do not round; the encoded funct3 selects the compare kind.