Is rd a floating-point register for FLE.D?
No. rd is an integer register holding the Boolean result 0 or 1.
FLE.D
RISC-V FLE.D Instruction Details
Instruction ManualR-typeDouble-precision floating-point less-or-equal comparison; writes x[rd]=1 when true, otherwise 0.
Instruction Syntax
fle.d rd, rs1, rs2
Operand Breakdown
rd: destination integer register receiving a 0 or 1 comparison result.
rs1/rs2: source floating-point registers; compare instructions do not use an rm rounding mode.
DFloating-Point Compare
Instruction Behavior
FLE.D compares the double-precision floating-point values in f[rs1] and f[rs2] and writes the Boolean result to integer register rd. It is a signaling comparison: any NaN, including a quiet NaN, sets NV and makes the result 0. The result is not a floating-point value and is not rounded by rm.
Quick Understanding & Search Notes
FLE.D writes the floating-point comparison result to integer register x[rd]. It has signaling-comparison semantics, so even a quiet NaN raises NV.
It writes 1 when rs1 <= rs2 is true, otherwise 0; any NaN operand writes 0.
The instruction does not produce a floating-point result and has no rm rounding field.
Common Usage Scenarios
Comparison & Detection
Understand this scenario with real code like «fle.d x10, f0, f1 # x10 = (f0<=f1)».
Floating-Point Conditions
Understand this scenario with real code like «fle.d x10, f0, f1 # x10 = (f0<=f1)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Signaling comparisons set NV for any NaN; this differs from FEQ and Zfa quiet comparisons.
rd is an integer register and receives 0 or 1, not a floating-point value.
The comparison does not use the rm rounding mode.
FAQ
What happens on NaN operands?
Any NaN operand makes the result 0 and sets NV.