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FLE.S

RISC-V FLE.S Instruction Details

Instruction ManualR-type

single-precision floating-point less-or-equal compare; writes the 0/1 Boolean result to integer register rd.

Instruction Syntax

fle.s rd, rs1, rs2

Operand Breakdown

rd: destination integer register receiving a 0 or 1 comparison result.

rs1/rs2: source floating-point registers; compare instructions do not use an rm rounding mode.

FFloating-Point Compare

Related Search Terms

fle.s instruction RISC-V fle.s fle.s syntax fle.s encoding fle.s NaN rules fle.s NV flag single-precision FP less-or-equal compare

Instruction Behavior

FLE.S compares the single-precision floating-point values in f[rs1] and f[rs2], then writes the Boolean result to integer register rd. FLE is a signaling comparison: any NaN makes the result 0 and sets NV. The comparison result is not a floating-point value and the instruction has no rm operand.

FLE.S Decode And Execute Animation

Shows the F-extension single-precision OP-FP flow: decode fields, read FP operands, perform FLE semantics, then write rd.

rs1

rs2

fle.s

Execution Context

FLEN>=32 / fmt=S (00)

funct3: less-or-equal compare

fflags: initial 0

fa1(f11) valueExact whitelist: -3.5, -2, 0, 0.5, 1, 1.25, 1.5, 2, 2.25, 3, 3.5, 3.75, 5.25, 7, 7.5, 8; also signed zeros, qnan, snan, inf, -inffa2(f12) valueExact whitelist: -3.5, -2, 0, 0.5, 1, 1.25, 1.5, 2, 2.25, 3, 3.5, 3.75, 5.25, 7, 7.5, 8; also signed zeros, qnan, snan, inf, -inf

31..27

26..25

24..20

19..15

14..12

11..7

6..0

10100

FLE

fmt=S

01100

rs2

01011

rs1

000

funct3=000

01010

1010011

OP-FP

Execution Data Path

instruction

0xA0C58553

opcode

1010011 -> OP-FP

funct5/fmt

10100 + S(00) -> FLE.S

funct3

000 -> less-or-equal compare

rd/rs

a0(x10) / fa1(f11) / fa2(f12)

read

Source registers not read yet

FP op

Awaiting Execute

write

Not written yet; initial fflags=0

Current Step

Fetch: show the 32-bit OP-FP encoding

The word is split as an R-type OP-FP instruction; single-precision OP-FP instructions use opcode 1010011.

encoding: 0xA0C58553

syntax : fle.s a0(x10), fa1(f11), fa2(f12)

result : Not written yet; initial fflags=0

The comparison result is written to integer register x[rd] and is only 0 or 1; compare instructions do not use rm.

Single-precision Calculation

rs1

fa1(f11) = 1.5

rs2

fa2(f12) = 2.25

result

Awaiting Execute

The comparison result is written to integer register x[rd] and is only 0 or 1; compare instructions do not use rm.

Assumes required extensions and FS enabled, valid NaN-boxing, and initial fflags=0. Finite inputs use the exact whitelist; signed zeros, infinities, qNaN, and sNaN are supported. Other inputs stop execution. One source register must have one initial value; rd=x0 discards only the integer write while NV still accrues. Steps are teaching views.

This animation shows only F-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.

Quick Understanding & Search Notes

FLE.S bridges FP comparison to an integer Boolean result: it reads two FP registers but writes x[rd]=0/1.

FLE.S requires F; funct5=10100, fmt=00, and funct3=000 in bits [14:12] select single-precision FLE.

Any NaN produces result 0 and sets NV.

rd is an integer register; bits [14:12] are the comparison-selecting funct3, not an rm rounding field, and assembly syntax has no rm operand.

Applies to RV32/RV64 F (depends on Zicsr); FLEN≥32. Required extensions and FP state must be enabled; sources narrower than FLEN require valid NaN-boxing, otherwise they are read as canonical qNaN.

With rd=x0, the integer result is discarded and x0 stays 0; NV raised by a NaN still accrues in fflags.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, §21.8

Common Usage Scenarios

Comparison & Detection

Understand this scenario with real code like «fle.s x10, f0, f1 # f0=1.5, f1=2.25 -> x10=1; initial fflags=0, final fflags=0».

Floating-Point Conditions

Understand this scenario with real code like «fle.s x10, f0, f1 # f0=1.5, f1=2.25 -> x10=1; initial fflags=0, final fflags=0».

Pre-Use Checklist

Syntax Check

rd: destination integer register receiving a 0 or 1 comparison result.
rs1/rs2: source floating-point registers; compare instructions do not use an rm rounding mode.

Semantic Check

Confirm the result is written to an integer register and is only 0 or 1.
Confirm quiet/signaling comparison behavior for NaNs and NV matches the need.

Pitfalls / Common Confusions

FLE is a signaling comparison, so any NaN sets NV and produces result 0.

rd is an integer register and receives 0 or 1, not a floating-point register.

The comparison has no rm field and performs no floating-point rounding.

FAQ

Is rd a floating-point register for FLE.S?

No. rd is an integer register holding the Boolean result 0 or 1.

How does FLE.S handle NaN operands?