Is rd a floating-point register for FEQ.S?
No. rd is an integer register holding the Boolean result 0 or 1.
FEQ.S
RISC-V FEQ.S Instruction Details
Instruction ManualR-typeSingle-precision floating-point equality compare; writes the 0/1 Boolean result to integer register rd.
Instruction Syntax
feq.s rd, rs1, rs2
32-bit OP-FP: funct5[31:27]=10100, fmt[26:25]=00, rs2[24:20], rs1[19:15], funct3[14:12]=010, rd[11:7], opcode[6:0]=1010011; no rm.
rd is integer x0–x31 and rs1/rs2 are FP f0–f31; ABI names are accepted. x0 discards the Boolean result while NV still accrues. Integer and FP registers with the same index belong to separate register files.
Applies to RV32/RV64 F, FLEN≥32; enable required extensions and FP state. Sources narrower than FLEN require valid NaN-boxing, otherwise they are read as canonical qNaN.
Write 1 for equality, otherwise 0; any NaN writes 0. Only sNaN sets NV; qNaN neither sets NV nor clears old NV. fflags accrues exceptions; flag setting alone causes no base FP exception trap.
One source register must have one initial value. The animation starts with fflags=0 and accepts only listed exact finite values plus signed zeros, infinities, qNaN, and sNaN. Steps are teaching views.
FFloating-Point Compare
Instruction Behavior
FEQ.S compares the single-precision floating-point values in f[rs1] and f[rs2], then writes the Boolean result to integer register rd. FEQ is a quiet comparison: a quiet NaN makes the result 0 without setting NV, while a signaling NaN sets NV. The comparison result is not a floating-point value; bits[14:12] are funct3=010 selecting EQ, not an rm rounding mode.
FEQ.S Decode And Execute Animation
Shows the F-extension single-precision OP-FP flow: decode fields, read FP operands, perform FEQ semantics, then write rd.
rd
rs1
rs2
feq.s
,
,
Execution Context
FLEN>=32 / fmt=S (00)
funct3: equality compare
fflags: initial 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
10100
FEQ
00
fmt=S
01100
rs2
01011
rs1
010
funct3=010
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xA0C5A553
opcode
1010011 -> OP-FP
funct5/fmt
10100 + S(00) -> FEQ.S
funct3
010 -> equality compare
rd/rs
a0(x10) / fa1(f11) / fa2(f12)
read
Source registers not read yet
FP op
Awaiting Execute
write
Not written yet; initial fflags=0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; single-precision OP-FP instructions use opcode 1010011.
encoding: 0xA0C5A553
syntax : feq.s a0(x10), fa1(f11), fa2(f12)
result : Not written yet; initial fflags=0
The comparison result is written to integer register x[rd] and is only 0 or 1; compare instructions do not use rm.
Single-precision Calculation
rs1
fa1(f11) = 1.5
rs2
fa2(f12) = 1.5
result
Awaiting Execute
The comparison result is written to integer register x[rd] and is only 0 or 1; compare instructions do not use rm.
Assumes required extensions and FS enabled, valid NaN-boxing, and initial fflags=0. Finite inputs use the exact whitelist; signed zeros, infinities, qNaN, and sNaN are supported. Other inputs stop execution. One source register must have one initial value; rd=x0 discards only the integer write while NV still accrues. Steps are teaching views.
This animation shows only F-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
Quick Understanding & Search Notes
FEQ.S bridges FP comparison to an integer Boolean result: it reads two FP registers but writes x[rd]=0/1.
funct5=10100 and funct3=010 select FEQ, while fmt=00 selects the S format.
Any NaN produces result 0; quiet NaN does not set or clear NV, while signaling NaN sets NV.
rd is an integer register; bits[14:12] are funct3=010, not an rm rounding mode.
Common Usage Scenarios
Comparison & Detection
Understand this scenario with real code like «feq.s x10, f0, f1 # x10 = (f0==f1)».
Floating-Point Conditions
Understand this scenario with real code like «feq.s x10, f0, f1 # x10 = (f0==f1)».
Pre-Use Checklist
Syntax Check
- rd: destination integer register receiving a 0 or 1 comparison result.
- rs1/rs2: source floating-point registers; compare instructions do not use an rm rounding mode.
Semantic Check
- Confirm the result is written to an integer register and is only 0 or 1.
- Confirm quiet/signaling comparison behavior for NaNs and NV matches the need.
Pitfalls / Common Confusions
FEQ sets NV only for sNaN; qNaN produces 0 without clearing an existing NV.
rd is an integer register and receives 0 or 1, not a floating-point register.
bits[14:12] are funct3=010 selecting EQ, not an rm rounding mode; the comparison performs no floating-point rounding.
fflags accrues exception flags; rd=x0 discards only the integer write, retaining NV side effects.
FAQ
How does FEQ.S handle NaN operands?
Any NaN produces result 0; FEQ sets NV only for signaling NaN.
Does FEQ.S use rm rounding?
No. FP comparisons do not round; the encoded funct3 selects the compare kind.