How is FMADD.Q different from FMUL plus add/subtract?
FMADD.Q is fused: the product is not first rounded into an intermediate FP result; the whole expression is rounded once at the end according to rm.
FMADD.Q
RISC-V FMADD.Q Instruction Details
Instruction ManualR4-typequad-precision fused multiply-add: rd = (rs1 * rs2) + rs3, with one final rounding according to rm.
Instruction Syntax
fmadd.q rd, rs1, rs2, rs3[, rm]
Operand Breakdown
rd: destination floating-point register.
rs1, rs2, rs3: three source floating-point registers; R4 is not an ordinary three-register R-type form.
rm: rounding-mode field for the final fused multiply-add/subtract result.
QFloating-Point Arithmetic
Instruction Behavior
FMADD.Q uses the R4 four-register format for quad-precision fused multiply-add. The rs1*rs2 product is not rounded or written as an intermediate result; it is combined with rs3 as one fused expression, rounded once according to rm, and written to rd.
FMADD.Q Decode And Execute Animation
Shows the Q-extension quad-precision R4 fused multiply-add flow: decode fields, read FP operands, perform FMADD semantics, then write rd.
rd
rs1
rs2
rs3
rm
fmadd.q
,
,
,
,
Leave rm empty to use the assembly default dyn encoding and fcsr.frm below.
Execution Context
FLEN=128 / fmt=Q (11)
rounding: RNE nearest-even
fflags: initial 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
01101
rs3
11
fmt=Q
01100
rs2
01011
rs1
000
rm
01010
rd
1000011
MADD
Execution Data Path
instruction
0x6EC58543
opcode
1000011 -> MADD
rs3/fmt
fa3(f13) + Q(11) -> R4 FMADD
rm
000 -> RNE nearest-even
rd/rs
fa0(f10) / fa1(f11) / fa2(f12) / fa3(f13)
read
Source registers not read yet
fused op
Awaiting Execute
write
Not written yet; initial fflags=0
Current Step
Fetch: show the 32-bit R4 encoding
The word is split as an R4-type instruction; FMADD.Q uses its dedicated major opcode 1000011, not the ordinary OP-FP opcode.
encoding: 0x6EC58543
syntax : fmadd.q fa0(f10), fa1(f11), fa2(f12), fa3(f13), rne
result : Not written yet; initial fflags=0
The default example (1.5 * 2.0) + 0.5 = 3.5 is exactly checkable; the fused operation rounds once at the end, so example fflags remains 0.
Quad-precision Calculation
rs1
fa1(f11) = 1.5
rs2
fa2(f12) = 2.0
rs3
fa3(f13) = 0.5
result
Awaiting Execute
The default example (1.5 * 2.0) + 0.5 = 3.5 is exactly checkable; the fused operation rounds once at the end, so example fflags remains 0.
Assumes the extension is available, FS enabled, correctly NaN-boxed inputs, and initial fflags=0. Only nonzero finite exact whitelisted inputs and nonzero whitelisted results are accepted; zero and rounding/exception boundaries are outside this animation. One source register must have one initial value; rd may overlap a source, and f0 accepts writeback. Steps are teaching views.
This animation shows only Q-extension ISA-visible R4 encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
Quick Understanding & Search Notes
FMADD.Q adds rs3 to rs1×rs2 with one final rounding; rs3 is a separately encoded third source register.
R4 major opcode=1000011 identifies the MADD fused operation class, and fmt=Q selects the quad-precision format.
The encoded field order is rs3 | fmt | rs2 | rs1 | rm | rd | opcode; this differs from ordinary OP-FP R-type instructions.
The semantic expression is rd = (rs1 * rs2) + rs3, and the fused operation is rounded once at the end according to rm/frm.
The animation executes only nonzero finite exact whitelist inputs with a whitelisted result; special values, rounding boundaries, and exception paths are not simulated.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — 21.2–21.6: rounding, flags, FMA and FMIN/FMAXThe RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — 22.2: NaN-boxingThe RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — 23.2: Q computational instructionsRISC-V Assembly Programmer's Manual — Floating-point rounding modes
Common Usage Scenarios
Fused Floating Point
Understand this scenario with real code like «fmadd.q f0, f1, f2, f3, rne # f1=1.5, f2=2, f3=0.5 -> f0=3.5».
Numerical Computing
Understand this scenario with real code like «fmadd.q f0, f1, f2, f3, rne # f1=1.5, f2=2, f3=0.5 -> f0=3.5».
Pre-Use Checklist
Syntax Check
- rd: destination floating-point register.
- rs1, rs2, rs3: three source floating-point registers; R4 is not an ordinary three-register R-type form.
- rm: rounding-mode field for the final fused multiply-add/subtract result.
Semantic Check
- Confirm rs3 participates in the fused operation and the result is rounded only once at the end.
- Confirm the sign rules for FNMADD/FNMSUB match the intended operation.
Pitfalls / Common Confusions
FMADD.Q is a fused operation, not the same as FMUL followed by FADD/FSUB with two roundings.
In the R4 encoding, bits 31..27 are the rs3 field; do not decode them as an ordinary OP-FP R-type funct5 field.
rm=101/110 is reserved; rm=111 uses frm, whose values 101–111 give reserved behavior. Omitting rm defaults to dyn in assembly.
Infinity times zero sets NV even when rs3 is a quiet NaN; applicable exception flags accrue in fflags.
FAQ
Why is FMADD.Q R4-type?
It needs rd, rs1, rs2, rs3, and rm fields; bits 31..27 hold rs3, not an ordinary R-type funct5 field.
Can FMADD.Q set fflags?
Applicable NV, OF, UF, and NX accrue in fflags. Exact teaching examples assume initial fflags=0 and add no flags.