How is FNMSUB.Q different from FMUL plus add/subtract?
FNMSUB.Q is fused: the product is not first rounded into an intermediate FP result; the whole expression is rounded once at the end according to rm.
FNMSUB.Q
RISC-V FNMSUB.Q Instruction Details
Instruction ManualR4-typequad-precision negated fused multiply-subtract: rd = -(rs1 * rs2) + rs3, with one final rounding according to rm.
Instruction Syntax
fnmsub.q rd, rs1, rs2, rs3[, rm]
Operand Breakdown
rd, rs1, rs2, rs3: FP registers f0–f31 or ABI names; f0 is writable, and overlapping sources read one initial value before writeback.
Optional rm defaults to dyn; use lowercase rne/rtz/rdn/rup/rmm/dyn, with 111 selecting frm. Static 101/110 and dynamic frm=101–111 have reserved behavior.
QFloating-Point Arithmetic
Instruction Behavior
FNMSUB.Q uses R4 to compute -(rs1×rs2)+rs3. The product is not separately rounded; rm rounds the final fused expression once to a 128-bit quad-precision result in FP register rd. It supports RV32/RV64 with Q and enabled FP state.
FNMSUB.Q Decode And Execute Animation
Shows the Q-extension quad-precision R4 negated fused multiply-subtract flow: decode fields, read FP operands, perform FNMSUB semantics, then write rd.
rd
rs1
rs2
rs3
rm
fnmsub.q
,
,
,
,
Leave rm empty to use the assembly default dyn encoding and fcsr.frm below.
Execution Context
FLEN=128 / fmt=Q (11)
rounding: RNE nearest-even
fflags: initial 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
01101
rs3
11
fmt=Q
01100
rs2
01011
rs1
000
rm
01010
rd
1001011
NMSUB
Execution Data Path
instruction
0x6EC5854B
opcode
1001011 -> NMSUB
rs3/fmt
fa3(f13) + Q(11) -> R4 FNMSUB
rm
000 -> RNE nearest-even
rd/rs
fa0(f10) / fa1(f11) / fa2(f12) / fa3(f13)
read
Source registers not read yet
fused op
Awaiting Execute
write
Not written yet; initial fflags=0
Current Step
Fetch: show the 32-bit R4 encoding
The word is split as an R4-type instruction; FNMSUB.Q uses its dedicated major opcode 1001011, not the ordinary OP-FP opcode.
encoding: 0x6EC5854B
syntax : fnmsub.q fa0(f10), fa1(f11), fa2(f12), fa3(f13), rne
result : Not written yet; initial fflags=0
The default example -(1.5 * 2.0) + 1.0 = -2.0 is exactly checkable; the fused operation rounds once at the end, so example fflags remains 0.
Quad-precision Calculation
rs1
fa1(f11) = 1.5
rs2
fa2(f12) = 2.0
rs3
fa3(f13) = 1.0
result
Awaiting Execute
The default example -(1.5 * 2.0) + 1.0 = -2.0 is exactly checkable; the fused operation rounds once at the end, so example fflags remains 0.
Assumes the extension is available, FS enabled, correctly NaN-boxed inputs, and initial fflags=0. Only nonzero finite exact whitelisted inputs and nonzero whitelisted results are accepted; zero and rounding/exception boundaries are outside this animation. One source register must have one initial value; rd may overlap a source, and f0 accepts writeback. Steps are teaching views.
This animation shows only Q-extension ISA-visible R4 encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
Quick Understanding & Search Notes
FNMSUB.Q's key points are R4 encoding and fused semantics: rs3 is a real third source register, and the product plus/minus term forms one exact intermediate expression that is rounded only once.
Requires RV32/RV64 Q and enabled FP state, with 128-bit quad-precision operands and results. Q depends on D and sets FLEN=128.
32-bit R4: rs3[31:27] | fmt=11[26:25] | rs2[24:20] | rs1[19:15] | rm[14:12] | rd[11:7] | opcode=1001011[6:0].
rd, rs1, rs2 and rs3 select FP registers f0–f31; f0 is writable. rs3 is a third source, not an implicit old value of rd.
Optional rm defaults to dyn: 000/001/010/011/100 select rne/rtz/rdn/rup/rmm; 111 uses frm. Static 101/110 and dynamic frm=101–111 have reserved behavior.
Operands narrower than FLEN must be correctly NaN-boxed; otherwise they are treated as canonical NaNs in their format. Narrower results get upper FLEN bits set to ones.
Applicable NV, OF, UF and NX accrue in fflags; setting a flag does not itself cause an FP exception trap. Infinity times zero must set NV even if rs3 is a quiet NaN; NaN results use canonical NaN by default.
Negate the product, then add rs3. Do not infer signed-zero or directed-rounding results by separately fusing a subtraction and then negating it. The animation accepts only finite exact-whitelist inputs and nonzero exact-whitelist results, assuming valid NaN-boxing and initial fflags=0.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — F 2.2, §§21.2–21.6The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Q 2.2RISC-V Assembly Programmer's Manual — Floating-point rounding modesRISC-V ABIs Specification — Version 1.0, floating-point register convention
Common Usage Scenarios
Fused Floating Point
Assume required extensions and FP state enabled, f1=1.5, f2=2 and f3=1 in this format (validly NaN-boxed when narrower than FLEN), and initial fflags=0: the example writes the exact result f0=-(1.5×2)+1=-2; fflags remains 0.
Numerical Computing
Assume required extensions and FP state enabled, f1=1.5, f2=2 and f3=1 in this format (validly NaN-boxed when narrower than FLEN), and initial fflags=0: the example writes the exact result f0=-(1.5×2)+1=-2; fflags remains 0.
Pre-Use Checklist
Syntax Check
- rd, rs1, rs2, rs3: FP registers f0–f31 or ABI names; f0 is writable, and overlapping sources read one initial value before writeback.
- Optional rm defaults to dyn; use lowercase rne/rtz/rdn/rup/rmm/dyn, with 111 selecting frm. Static 101/110 and dynamic frm=101–111 have reserved behavior.
Semantic Check
- Confirm the source format and required extensions match and FP state is enabled; formats narrower than FLEN require valid NaN-boxing.
- Applicable NV, OF, UF, and NX accrue in fflags, without DZ; setting exception flags does not itself trap.
Pitfalls / Common Confusions
FNMSUB.Q is a fused operation, not the same as FMUL followed by FADD/FSUB with two roundings.
In the R4 encoding, bits 31..27 are the rs3 field; do not decode them as an ordinary OP-FP R-type funct5 field.
rm controls the single final rounding; inexact, overflow, underflow, invalid-operation, and special-value paths are recorded by the official FP exception-flag rules.
The FNMSUB/FNMADD sign rules are easy to confuse: FNMSUB is -(rs1*rs2)+rs3, while FNMADD is -(rs1*rs2)-rs3.
FAQ
Why is FNMSUB.Q R4-type?
It needs rd, rs1, rs2, rs3, and rm fields; bits 31..27 hold rs3, not an ordinary R-type funct5 field.
Can FNMSUB.Q set fflags?
It can accrue NV, OF, UF and NX without clearing existing flags. Infinity times zero sets NV even with a quiet-NaN third source. The exact default example assumes initial fflags=0, so it remains 0.