How is FMSUB.Q different from FMUL plus add/subtract?
FMSUB.Q is fused: the product is not first rounded into an intermediate FP result; the whole expression is rounded once at the end according to rm.
FMSUB.Q
RISC-V FMSUB.Q Instruction Details
Instruction ManualR4-typequad-precision fused multiply-subtract: rd = (rs1 * rs2) - rs3, with one final rounding according to rm.
Instruction Syntax
fmsub.q rd, rs1, rs2, rs3, rm
Operand Breakdown
rd, rs1, rs2, rs3: FP registers f0–f31 or their ABI names; f0 is writable, rd may overlap a source, and overlapping sources read one initial value.
Optional lowercase rm defaults to dyn; rm=111 uses frm. Static 101/110 and dynamic frm=101–111 have reserved behavior.
QFloating-Point Arithmetic
Instruction Behavior
FMSUB.Q uses the R4 four-register format for quad-precision fused multiply-subtract. The rs1*rs2 product is not rounded or written as an intermediate result; it is combined with rs3 as one fused expression, rounded once according to rm, and written to rd.
FMSUB.Q Decode And Execute Animation
Shows the Q-extension quad-precision R4 fused multiply-subtract flow: decode fields, read FP operands, perform FMSUB semantics, then write rd.
rd
rs1
rs2
rs3
rm
fmsub.q
,
,
,
,
Leave rm empty to use the assembly default dyn encoding and fcsr.frm below.
Execution Context
FLEN=128 / fmt=Q (11)
rounding: RNE nearest-even
fflags: initial 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
01101
rs3
11
fmt=Q
01100
rs2
01011
rs1
000
rm
01010
rd
1000111
MSUB
Execution Data Path
instruction
0x6EC58547
opcode
1000111 -> MSUB
rs3/fmt
fa3(f13) + Q(11) -> R4 FMSUB
rm
000 -> RNE nearest-even
rd/rs
fa0(f10) / fa1(f11) / fa2(f12) / fa3(f13)
read
Source registers not read yet
fused op
Awaiting Execute
write
Not written yet; initial fflags=0
Current Step
Fetch: show the 32-bit R4 encoding
The word is split as an R4-type instruction; FMSUB.Q uses its dedicated major opcode 1000111, not the ordinary OP-FP opcode.
encoding: 0x6EC58547
syntax : fmsub.q fa0(f10), fa1(f11), fa2(f12), fa3(f13), rne
result : Not written yet; initial fflags=0
The default example (1.5 * 2.0) - 1.0 = 2.0 is exactly checkable; the fused operation rounds once at the end, so example fflags remains 0.
Quad-precision Calculation
rs1
fa1(f11) = 1.5
rs2
fa2(f12) = 2.0
rs3
fa3(f13) = 1.0
result
Awaiting Execute
The default example (1.5 * 2.0) - 1.0 = 2.0 is exactly checkable; the fused operation rounds once at the end, so example fflags remains 0.
Assumes the extension is available, FS enabled, correctly NaN-boxed inputs, and initial fflags=0. Only nonzero finite exact whitelisted inputs and nonzero whitelisted results are accepted; zero and rounding/exception boundaries are outside this animation. One source register must have one initial value; rd may overlap a source, and f0 accepts writeback. Steps are teaching views.
This animation shows only Q-extension ISA-visible R4 encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
Quick Understanding & Search Notes
FMSUB.Q's key points are R4 encoding and fused semantics: rs3 is a real third source register, and the product plus/minus term forms one exact intermediate expression that is rounded only once.
R4 major opcode=1000111 identifies the MSUB fused operation class, and fmt=Q selects the quad-precision format.
The encoded field order is rs3 | fmt | rs2 | rs1 | rm | rd | opcode; this differs from ordinary OP-FP R-type instructions.
The semantic expression is rd = (rs1 * rs2) - rs3, and the fused operation is rounded once at the end according to rm/frm.
Q depends on D and F, with FLEN=128. Available on RV32/RV64 with the required extensions and enabled FP state.
rd and all sources are FP registers f0–f31; f0 is writable. Overlapping sources read one initial value before writeback, and rd may overlap a source.
Q operations read and write 128-bit FP values without implicitly converting narrower formats.
The optional assembly rm operand must be lowercase and defaults to dyn. The animation starts with fflags=0 and accepts only nonzero finite exact whitelisted inputs and results. Special values, zero results, and rounding boundaries are not executed; steps are not processor cycles.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture (Version 20260120)The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture (Version 20260120)The RISC-V Instruction Set Manual, Volume II: Privileged Architecture (Version 20260120)RISC-V Assembly Programmer’s Manual (Version v0.0.0, 2025-02-05; release v0.0.1)RISC-V ABIs Specification (v1.0)
Common Usage Scenarios
Fused Floating Point
Understand this scenario with real code like «fmsub.q f0, f1, f2, f3, rne # f1=1.5, f2=2, f3=1 => f0=2».
Numerical Computing
Understand this scenario with real code like «fmsub.q f0, f1, f2, f3, rne # f1=1.5, f2=2, f3=1 => f0=2».
Pre-Use Checklist
Syntax Check
- rd, rs1, rs2, rs3: FP registers f0–f31 or their ABI names; f0 is writable, rd may overlap a source, and overlapping sources read one initial value.
- Optional lowercase rm defaults to dyn; rm=111 uses frm. Static 101/110 and dynamic frm=101–111 have reserved behavior.
Semantic Check
- Confirm the source format and required extensions match and FP state is enabled; formats narrower than FLEN require valid NaN-boxing.
- Applicable NV, OF, UF, and NX accrue in fflags, without DZ; setting exception flags does not itself trap.
Pitfalls / Common Confusions
FMSUB.Q is a fused operation, not the same as FMUL followed by FADD/FSUB with two roundings.
In the R4 encoding, bits 31..27 are the rs3 field; do not decode them as an ordinary OP-FP R-type funct5 field.
rm controls the single final rounding; rm=101 and 110 are reserved, while rm=111 selects frm and frm=101 through 111 gives reserved behavior.
If one multiplicand is infinity and the other is zero, NV must be set even when rs3 is a quiet NaN; other applicable OF, UF, and NX conditions also accrue in fflags.
The FNMSUB/FNMADD sign rules are easy to confuse: FNMSUB is -(rs1*rs2)+rs3, while FNMADD is -(rs1*rs2)-rs3.
FAQ
Why is FMSUB.Q R4-type?
It needs rd, rs1, rs2, rs3, and rm fields; bits 31..27 hold rs3, not an ordinary R-type funct5 field.
Can FMSUB.Q set fflags?
It can set FP exception flags under the official FP rules, such as inexact, overflow, underflow, or invalid operation; the default animation uses exact finite values, so it shows fflags remaining 0.