Is FMVH.X.D an FCVT conversion?
No. It only copies the bit pattern and does not interpret and convert the numeric value.
FMVH.X.D
RISC-V FMVH.X.D Instruction Details
Instruction ManualR-typeOn RV32, copy the high 32 bits of a double floating-point register to an integer register.
Instruction Syntax
fmvh.x.d rd, rs1
Operand Breakdown
rd/rs fields denote integer or floating-point registers depending on the direction of this instruction.
FMV forms copy bit patterns; they are not FCVT numeric conversions and do not use rm.
ZfaDData Movement
Instruction Behavior
FMVH.X.D is a Zfa bit-move instruction for RV32+D that copies bits 63:32 of f[rs1] into x[rd]. Together with FMV.X.W it can split a double-precision encoding into two integer registers; this is a bit copy, not a numeric conversion.
FMVH.X.D Decode And Execute Animation
Shows the Zfa + D (RV32 only)-extension FMVH.X.D bit-pattern move: decode OP-FP fields, read the source bit pattern, then write the destination without numeric conversion.
rd
rs1
fmvh.x.d
,
Execution Context
fmt=D (01)
FLEN>=64
31..27
26..25
24..20
19..15
14..12
11..7
6..0
11100
funct5=to-x
01
fmt=D
00001
rs2=00001
01011
rs1
000
funct3=000
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xE2158553
opcode
1010011 -> OP-FP
funct5/fmt
11100 + 01 -> funct7 1110001
rs2
00001 fixed for FMVH.X.D
rd/rs1
a0(x10) / fa1(f11)
read bits
fa1(f11) = 0xC00921FB54442D18
bit move
copy FP bits63:32 -> 0xC00921FB
write
a0(x10) = 0xC00921FB; fflags unchanged
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FMV bit moves use opcode 1010011.
encoding: 0xE2158553
syntax : fmvh.x.d a0(x10), fa1(f11)
result : a0(x10) = 0xC00921FB; fflags unchanged
Bit-Pattern Move View
FP source bits
0xC00921FB54442D18
unchanged payload
0xC00921FB
writeback
a0(x10) = 0xC00921FB
FMVH.X.D is defined only for RV32+D+Zfa and copies f[rs1] bits 63:32 to x[rd]; paired with FMV.X.W, it transfers a double-precision bit pattern.
This animation shows only Zfa + D (RV32 only)-extension FMV ISA-visible encoding and bit-pattern movement; it does not model FPU pipelines, numeric FP interpretation, exception handling, or microarchitecture.
Quick Understanding & Search Notes
FMVH.X.D fills the RV32 path for moving a 64-bit double encoding through 32-bit integer registers. The key points are bit order and that it is not numeric conversion.
FMVH.X.D takes the high 32 bits; FMVP.D.X uses rs1 for the low 32 bits and rs2 for the high 32 bits.
These instructions do not use rm and do not alter NaN payloads.
Common Usage Scenarios
Floating-Point Bit Move
Understand this scenario with real code like «fmvh.x.d x10, f11 ; x10 = f11[63:32] (RV32 only)».
RV32 Double Data Movement
Understand this scenario with real code like «fmvh.x.d x10, f11 ; x10 = f11[63:32] (RV32 only)».
Pre-Use Checklist
Syntax Check
- rd/rs fields denote integer or floating-point registers depending on the direction of this instruction.
- FMV forms copy bit patterns; they are not FCVT numeric conversions and do not use rm.
Semantic Check
- Confirm this is bit copying, not floating/integer numeric conversion.
- Confirm destination direction, sign-extension, or NaN-boxing rules for this FMV variant.
Pitfalls / Common Confusions
Used for RV32+D double-precision bit movement; RV64 normally uses FMV.X.D/FMV.D.X.
This is a bit copy, not an FCVT numeric conversion.
It sets no floating-point exception flags.
FAQ
Why does FMVH.X.D emphasize RV32?
Because RV32 integer registers are only 32 bits wide, so a 64-bit double encoding must be moved in a pair.