Does FMV.X.D round?
No. It is only a bit move.
FMV.X.D
RISC-V FMV.X.D Instruction Details
Instruction ManualR-typeRV64 double-precision bit-pattern move from FP to integer register, with no numeric conversion.
Instruction Syntax
fmv.x.d rd, rs1
Operand Breakdown
rd/rs fields denote integer or floating-point registers depending on the direction of this instruction.
FMV forms copy bit patterns; they are not FCVT numeric conversions and do not use rm.
DFloating-Point Convert
Instruction Behavior
FMV.X.D moves the IEEE 754 double-precision 64-bit encoding between integer and floating-point registers. It does not modify transferred bits and preserves non-canonical NaN payloads; this form is defined only when XLEN>=64. It writes the double-precision encoding from f[rs1] to x[rd] and sets no FP exception flags.
Quick Understanding & Search Notes
FMV.X.D is for preserving or reinterpreting double-precision encoding bits; it is not an FCVT conversion.
Transferred bits are unchanged, including non-canonical NaN payloads.
The official D extension provides this 64-bit move form only when XLEN>=64.
Common Usage Scenarios
Comparison & Detection
Understand this scenario with real code like «fmv.x.d x10, f0 # x10 = bits of f0 (RV64)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
This is a bit-pattern move, not an integer/FP numeric conversion; use FCVT for conversion.
Defined only for XLEN>=64; RV32 has no FMV.D.X/FMV.X.D.
It sets no FP exception flags and does not canonicalize NaN payloads.
FAQ
How is FMV.X.D different from FCVT?
FMV preserves encoding bits; FCVT performs numeric conversion and may round or set exception flags.