Can FMV.X.D be used on RV32?
No. The official D extension defines FMV.X.D / FMV.D.X 64-bit integer/FP register moves only when XLEN>=64.
FMV.X.D
RISC-V FMV.X.D Instruction Details
Instruction ManualR-typeRV64 double-precision bit-pattern move from FP to integer register, with no numeric conversion.
Instruction Syntax
fmv.x.d rd, rs1
Operand Breakdown
rd/rs fields denote integer or floating-point registers depending on the direction of this instruction.
FMV forms copy bit patterns; they are not FCVT numeric conversions and do not use rm.
DFloating-Point Bit Move
Instruction Behavior
FMV.X.D moves the IEEE 754 double-precision 64-bit encoding between integer and floating-point registers. It does not modify transferred bits and preserves non-canonical NaN payloads; this form is defined only when XLEN>=64. It writes the double-precision encoding from f[rs1] to x[rd] and sets no FP exception flags.
FMV.X.D Decode And Execute Animation
Shows the D-extension FMV bit-pattern move: decode OP-FP fields, read the source bit pattern, then write the destination without numeric conversion.
rd
rs1
fmv.x.d
,
Execution Context
fmt=D (01)
FLEN>=64
31..27
26..25
24..20
19..15
14..12
11..7
6..0
11100
funct5=to-x
01
fmt=D
00000
rs2=00000
01011
rs1
000
funct3=000
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xE2058553
opcode
1010011 -> OP-FP
funct5/fmt
11100 + 01 -> funct7 1110001
rs2
00000 fixed for FMV.X.D
rd/rs1
a0(x10) / fa1(f11)
read bits
fa1(f11) = 0x400921FB54442D18
bit move
copy 64-visible bits -> 0x400921FB54442D18
write
a0(x10) = 0x400921FB54442D18; fflags unchanged
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FMV bit moves use opcode 1010011.
encoding: 0xE2058553
syntax : fmv.x.d a0(x10), fa1(f11)
result : a0(x10) = 0x400921FB54442D18; fflags unchanged
Bit-Pattern Move View
FP source bits
0x400921FB54442D18
unchanged payload
0x400921FB54442D18
writeback
a0(x10) = 0x400921FB54442D18
FMV.X.D is defined only when XLEN>=64 and writes the 64-bit double-precision encoding unchanged to the integer register without setting fflags.
This animation shows only D-extension FMV ISA-visible encoding and bit-pattern movement; it does not model FPU pipelines, numeric FP interpretation, exception handling, or microarchitecture.
Quick Understanding & Search Notes
FMV.X.D is defined only when XLEN>=64 and moves the 64-bit double-precision encoding unchanged into an integer register. It does not convert a double to an integer value and does not canonicalize NaN payloads.
In the D extension, this 64-bit move form requires XLEN>=64.
Transferred bits are unchanged, including non-canonical NaN payloads.
rm is not used; no rounding occurs and FP exception flags are not set.
Common Usage Scenarios
double bit inspection
Understand this scenario with real code like «fmv.x.d x10, f0 # x10 = bits of f0 (RV64)».
NaN payload preservation
Understand this scenario with real code like «fmv.x.d x10, f0 # x10 = bits of f0 (RV64)».
RV64 raw encoding debug
Understand this scenario with real code like «fmv.x.d x10, f0 # x10 = bits of f0 (RV64)».
Pre-Use Checklist
Syntax Check
- rd/rs fields denote integer or floating-point registers depending on the direction of this instruction.
- FMV forms copy bit patterns; they are not FCVT numeric conversions and do not use rm.
Semantic Check
- Confirm this is bit copying, not floating/integer numeric conversion.
- Confirm destination direction, sign-extension, or NaN-boxing rules for this FMV variant.
Pitfalls / Common Confusions
This is a bit-pattern move, not an integer/FP numeric conversion; use FCVT for conversion.
Defined only for XLEN>=64; RV32 has no FMV.D.X/FMV.X.D.
It sets no FP exception flags and does not canonicalize NaN payloads.
FAQ
How is FMV.X.D different from FCVT.L.D?
FMV.X.D preserves the 64-bit encoding bits; FCVT.L.D performs double-to-64-bit-integer numeric conversion, which can round and set fflags.