How is FMV.H.X different from FCVT?
FMV copies the bit pattern; FCVT performs numeric conversion, can round, and can set exception flags.
FMV.H.X
RISC-V FMV.H.X Instruction Details
Instruction ManualR-typeBit-copy low integer-register bits into a half-precision floating-point register.
Instruction Syntax
fmv.h.x rd, rs1
Operand Breakdown
rd/rs fields denote integer or floating-point registers depending on the direction of this instruction.
FMV forms copy bit patterns; they are not FCVT numeric conversions and do not use rm.
ZfhZfhminFloating-Point Bit Move
Instruction Behavior
Provided by Zfh or Zfhmin (each depends on F), FMV.H.X bit-copies the low 16 bits of x[rs1] into f[rd] and NaN-boxes the half-precision result in the floating-point register. This is a bit move, not a numeric conversion.
FMV.H.X Decode And Execute Animation
Shows the Zfh/Zfhmin-extension FMV.H.X bit-pattern move: decode OP-FP fields, read the source bit pattern, then write the destination without numeric conversion.
rd
rs1
fmv.h.x
,
Execution Context
fmt=H (10)
FLEN>=32; H payload=16
31..27
26..25
24..20
19..15
14..12
11..7
6..0
11110
funct5=to-f
10
fmt=H
00000
rs2=00000
01011
rs1
000
funct3=000
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xF4058553
opcode
1010011 -> OP-FP
funct5/fmt
11110 + 10 -> funct7 1111010
rs2
00000 fixed for FMV.H.X
rd/rs1
fa0(f10) / a1(x11)
read bits
a1(x11) = 0xC100
bit move
copy low 16 bits -> 0xC100; NaN-box in FP register
write
fa0(f10) = 0xC100; fflags unchanged
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FMV bit moves use opcode 1010011.
encoding: 0xF4058553
syntax : fmv.h.x fa0(f10), a1(x11)
result : fa0(f10) = 0xC100; fflags unchanged
Bit-Pattern Move View
integer low bits
0xC100
unchanged payload
0xC100
writeback
fa0(f10) = 0xC100
FMV.H.X takes only the low 16 integer-source bits and NaN-boxes the half-precision result in the FP register.
This animation shows only Zfh/Zfhmin-extension FMV ISA-visible encoding and bit-pattern movement; it does not model FPU pipelines, numeric FP interpretation, exception handling, or microarchitecture.
Quick Understanding & Search Notes
FMV.H.X's core idea is bit-pattern movement. Use FCVT for numeric conversion and rounding; use FMV forms when preserving NaN payloads or inspecting raw encodings.
FMV.H.X is provided by Zfh or Zfhmin; each depends on F.
FMV instructions do not use an rm field.
A bit move does not canonicalize NaNs or change the input according to numeric value.
Common Usage Scenarios
Floating-Point Bit Move
Understand this scenario with real code like «fmv.h.x f0, x10 # f0 receives a NaN-boxed copy of x10[15:0]».
Debugging Bit Patterns
Understand this scenario with real code like «fmv.h.x f0, x10 # f0 receives a NaN-boxed copy of x10[15:0]».
Pre-Use Checklist
Syntax Check
- rd/rs fields denote integer or floating-point registers depending on the direction of this instruction.
- FMV forms copy bit patterns; they are not FCVT numeric conversions and do not use rm.
Semantic Check
- Confirm this is bit copying, not floating/integer numeric conversion.
- Confirm destination direction, sign-extension, or NaN-boxing rules for this FMV variant.
Pitfalls / Common Confusions
This is a bit copy, not an FCVT numeric conversion.
It does not use rm and does not set fflags.
The integer source provides only the low bits needed by the destination format.
FAQ
Does FMV.H.X set fflags?
No. It is neither arithmetic nor numeric conversion.